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Urgent help with vhdl neeeded

dash8shamir — Sat, 07 Nov 2009 11:48:36 GMT

Hi people, I need help to produce a VHDL behavioral code for my final year project, I need to create a 256 point radix-2 fft processor on a spartan-3A DSP FPGA and I am so stuck using modelsim and XILINX 10.1, I have reached to this point the code is below anyone who can get out the syntax error and how to declare shared variable I would appreciate.......
-- THIS FILE DECLARES THE SIGNALS USED IN THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

package butter_lib is

signal ram_data,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,d18,d19,out_data : std_logic_vector(31 downto 0) := (others => '0') ;
signal data_rom , rom_ff : std_logic_vector(31 downto 0) ;
signal clock_main , reset , enbl , clock : std_logic := '0' ;
signal c0 , c1 , c2 , c3 , c0_c1 , c2_c3 , c0_c2 , c1_c3 : std_logic ;
signal c0_and,c1_and,c2_and,c3_and,c0_c1and,c2_c3and,c0_c2and,c1_c3and : std_logic ;
signal reset_count : std_logic ;
type state is (reset1 , reset2 , reset3 , reset4 , reset5 , reset6 , reset7) ;

signal final_sum : std_logic_vector (31 downto 0) := (others => '0') ;
signal shift , finish_sum , signbit , normalise , end_all , a_small , addsub ,sum_out2 , shift_done , done , num_rec , setbit , addpulse : std_logic := '0' ;
signal shift_outa , swap_num2 : std_logic_vector ( 31 downto 0 ) := (others => '0') ;
signal swap_num1 , sum_out : std_logic_vector (32 downto 0) := (others => '0') ;
signal sub2 : std_logic_vector (8 downto 0) := (others => '0') ;
signal suba : std_logic_vector (8 downto 0) := (others => '0') ;
signal exp : std_logic_vector (7 downto 0) := (others => '0') ;
signal rst , enswap , ensub , enshift , finsub , finswap , finshift , numzero : std_logic := '0' ;
signal zerodetect : std_logic_vector(1 downto 0) ;
signal changea : std_logic ;

signal final_sumb : std_logic_vector (31 downto 0) := (others => '0') ;
signal shiftb , finish_sumb , signbitb , normaliseb , end_allb , a_smallb , addsubb,sum_out2b , shift_doneb , doneb , num_recb , setbitb , addpulseb , clockb : std_logic := '0' ;
signal shift_outb , swap_num2b : std_logic_vector ( 31 downto 0 ) := (others => '0') ;
signal swap_num1b , sum_outb : std_logic_vector (32 downto 0) := (others => '0') ;
signal sub2b : std_logic_vector (8 downto 0) := (others => '0') ;
signal subb : std_logic_vector (8 downto 0) := (others => '0') ;
signal expb: std_logic_vector (7 downto 0) := (others => '0') ;
signal rstb , enswapb , ensubb , enshiftb , finsubb , finswapb , finshiftb , numzerob , clock_mainb , resetb , enblb : std_logic := '0' ;
signal zerodetectb : std_logic_vector(1 downto 0) ;
signal changeb : std_logic ;

signal incr , clear , io_mode , staged , iod : std_logic ;
signal butterfly,fftadd_rd,shift1,shift3,shift4,shift5,shift6,ram_wr,ram_rd,io_add : std_logic_vector(3 downto 0) := (others => '0') ;
signal fftd , fft_en , ip , op , init : std_logic ;
signal stage : std_logic_vector(1 downto 0) ;
--signal clock_main,c0,c1,c2,c3,c0_c1,c2_c3,c0_c2,c1_c3 : std_logic ;
signal preset,disable,c0_en,rom_en,romgen_en : std_logic ;
signal clk_count : std_logic_vector(2 downto 0) ;
signal enbw , enbor : std_logic ;
signal data_io : std_logic_vector(31 downto 0) := (others => '0') ;
signal rom_add : std_logic_vector(2 downto 0) ;
type state_values is (st0 , st1 , st2 , st3) ;
signal pres_state1 , next_state1 : state_values ;

signal butterfly_iod : std_logic_vector(3 downto 0) ;
signal cyc_clear : std_logic ;
signal add_rd , add_wr : std_logic_vector(3 downto 0) ;

end butter_lib ;

--THIS FILE RECEIVES THE OUTPUT OF THE WAVEFORM GENERATOR AND
--OUTPUTS THE REQUIRED CYCLES

library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.butter_lib.all ;

entity and_gates is
port (
waves_and : in std_logic_vector(3 downto 0) ;
clock_main , c0_en : in std_logic ;
c0,c1,c2,c3 : out std_logic ;
c0_c1,c2_c3,c0_c2,c1_c3 : out std_logic ) ;
end and_gates ;

architecture rtl of and_gates is
begin
process(clock_main,waves_and)
begin
if (c0_en = '1' and clock_main='1') then

c0 <= waves_and(3) ;
c1 <= waves_and(2) ;
c2 <= waves_and(1) ;
c3 <= waves_and(0) ;
c0_c1 <= waves_and(3) or waves_and(2) ;
c0_c2 <= waves_and(3) or waves_and(1) ;
c2_c3 <= waves_and(1) or waves_and(0) ;
c1_c3 <= waves_and(0) or waves_and(2) ;
else
c0 <= '0' ;
c1 <= '0' ;
c2 <= '0' ;
c3 <= '0' ;
c0_c1 <= '0' ;
c0_c2 <= '0' ;
c2_c3 <= '0' ;
c1_c3 <= '0' ;
end if ;
end process ;
end rtl ;
--BASE INDEX GENERATOR
library ieee;
use ieee.std_logic_1164.all;
use work.butter_lib.all ;

entity baseindex is
port(
ind_butterfly: in std_logic_vector(3 downto 0);
ind_stage: in std_logic_vector(1 downto 0);
add_fft: in std_logic;
fftadd_rd: out std_logic_vector(3 downto 0);
c0,c1,c2,c3: in std_logic);
end baseindex;

architecture rtl of baseindex is
begin
process(ind_butterfly,ind_stage,add_fft,c0,c1,c2,c3)
variable out_sig : std_logic_vector(3 downto 0);
begin
if (add_fft='1') then
if(c2='1') then -- address for 'x'. Since this is the real part,
case ind_stage is -- M.S.B is '0'.
when "00" => out_sig := "00" & ind_butterfly(1 downto 0);
when "01" => out_sig := '0' & ind_butterfly(1) & '0' & ind_butterfly(0);
-- when "10" => out_sig := '0' & '1' & '1' & ind_butterfly(3);
when "10" => out_sig := '0' & ind_butterfly(1 downto 0) & '0';
when others => out_sig := "0000";
end case;

elsif(c0='1') then -- address for 'y'.
case ind_stage is
when "00" => out_sig := "01" & ind_butterfly(1 downto 0);
when "01" => out_sig := '0' & ind_butterfly(1) & '1' & ind_butterfly(0);
when "10" => out_sig := '0' & ind_butterfly(1 downto 0) & '1';
when others => out_sig := "0000";
end case;

elsif(c1='1') then -- addresss for 'Y'
case ind_stage is
when "00" => out_sig := "11" & ind_butterfly(1 downto 0);
when "01" => out_sig := '1' & ind_butterfly(1) & '1' & ind_butterfly(0);
when "10" => out_sig := '1' & ind_butterfly(1 downto 0) & '1';
when others => out_sig := "0000";
end case;

elsif(c3='1') then -- address for 'X'
case ind_stage is
when "00" => out_sig := "10" & ind_butterfly(1 downto 0);
when "01" => out_sig := '1' & ind_butterfly(1) & '0' & ind_butterfly(0);
when "10" => out_sig := '1' & ind_butterfly(1 downto 0) & '0';
when others => out_sig := "0000";
--else
--out_sig := "ZZZZ";
end case;
end if;
end if;
fftadd_rd <= out_sig (3 downto 0) ;
end process;
end rtl;
-- BUTTERFLY GENERATOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity but_gen is
port (
add_incr , add_clear , stagedone : in std_logic ;
but_butterfly : out std_logic_vector(3 downto 0) ) ;
end but_gen ;

architecture rtl of but_gen is
begin
process(add_clear , add_incr , stagedone)
variable cnt : integer ;
variable count : std_logic_vector(3 downto 0) ;
begin
if(add_clear = '1' or stagedone = '1') then
count := "0000" ;
but_butterfly <= "0000" ;
elsif (add_incr'event and add_incr = '1') then
but_butterfly <= (count + 1) ;
count := count + 1 ;
end if ;
end process ;
end rtl ;

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;

entity control_main is
port (
a_small , sign_a , sign_b : in std_logic ;
sign_out , add_sub , reset_all : out std_logic ;
en_sub , en_swap , en_shift , addpulse , normalise : out std_logic ;
fin_sub , fin_swap , finish_shift , add_finish , end_all : in std_logic ;
clock_main , clock , reset , enbl , zero_num , change: in std_logic ) ;
end control_main ;

architecture rtl of control_main is
signal current_state , next_state : state ;
begin
process (current_state , add_finish , finish_shift , end_all , enbl , clock_main , fin_sub , fin_swap , zero_num , change)
begin

case current_state is
when reset1 =>
if( enbl = '1' and clock_main = '1') then
normalise <= '0' ;
addpulse <= '0' ;
reset_all <= '1' ;
next_state <= reset2 ;
elsif ( enbl = '0') then
next_state <= reset7 ;-- last state to exit
else
next_state <= reset1 ;
end if ;

when reset2 =>
reset_all <= '0' ; -- else values willnot cchange
en_sub <= '1' ;
en_swap <= '1' ;
next_state <= reset3 ;

when reset3 =>
if (zero_num = '1') then
next_state <= reset5 ;
en_sub <= '0' ;
en_swap <= '0' ;
elsif(fin_sub= '1') then
if(fin_swap = '1') then
en_shift <= '1' ;
en_sub <= '0' ;
en_swap <= '0' ;
next_state <= reset4 ;
end if ;
else
next_state <= reset3 ;
end if ;

when reset4 =>
if (finish_shift = '1') then
en_shift <= '0' ;
addpulse <= '1' ;
next_state <= reset5 ;
else
next_state <= reset4 ;
end if ;

when reset5 =>
if (zero_num = '1') then
normalise <= '1' ;
next_state <= reset6 ;
elsif (add_finish = '1') then
normalise <= '1' ;
addpulse <= '0' ;
next_state <= reset6 ;
else
next_state <= reset5 ;
end if ;

when reset6 =>
if (end_all = '1' and clock_main = '1') then
normalise <= '0' ;
next_state <= reset6 ;
elsif (end_all = '1' and clock_main = '0') then
next_state <= reset1 ;
else
next_state <= reset6 ;
end if ;

when reset7 =>
next_state <= reset7 ;

when others =>
next_state <= reset1 ;

end case ;
end process ;

process(clock , reset , change)
begin
if(change = '1') then
current_state <= reset1 ;
elsif (reset = '1') then
current_state <= reset1 ;
elsif (clock= '1' and clock'event) then
current_state <= next_state ;
end if ;
end process ;

process (a_small , sign_a , sign_b)
begin
if (sign_a = '0' and sign_b = '0') then
sign_out <= '0' ;
add_sub <= '1' ;

elsif (sign_a = '1' and sign_b = '1') then
sign_out <= '1' ;
add_sub <= '1' ;

elsif (a_small = '1' and sign_a = '0') then
sign_out <= '1' ;
add_sub <= '0' ;

elsif (a_small = '0' and sign_a = '1') then
sign_out <= '1' ;
add_sub <= '0' ;

else
sign_out <= '0' ;
add_sub <= '0' ;
end if ;

end process ;

end rtl ;
-- THIS FILE COUNTS THE NUMBER OF CYCLES AFTER FFT COMPUTATION IS ENABLED.
-- THIS IS REQUIRED BECAUSE WRITING INTO THE RAM BEGINS ONLY AFTER 5 CYCLES (DURING C1)
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity counter is
port (
c : out std_logic_vector(2 downto 0) ;
disable , clock_main , reset : in std_logic) ;
end counter ;

architecture rtl of counter is
begin
process (reset , clock_main , disable)
variable temp : std_logic_vector(2 downto 0) ;
begin
if (disable <= '0') then
if(reset = '1') then
c <= "000" ;
temp := "000" ;
elsif(clock_main = '1' and clock_main'event) then
c <= (temp + 1) ;
temp := temp + 1 ;
end if ;
end if ;
end process ;
end rtl ;
-- POSITIVE EDGE TRIGGERED FLIPFLOPS PLACED BEFORE THE DIVIDE BY TWO UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity level_edge is
port (
data_edge : in std_logic_vector(31 downto 0) ;
trigger_edge : in std_logic ;
edge_out : out std_logic_vector(31 downto 0) ) ;
end level_edge ;

architecture rtl of level_edge is
begin
process(data_edge , trigger_edge)
begin
if (trigger_edge='1' and trigger_edge'event) then
edge_out <= data_edge(31 downto 0) ;
end if ;
end process ;
end rtl ;
-- DIVIDE BY TWO UNIT. THIS FILE HOWEVER PASSED THE DATA UNCHANGED
-- BECAUSE DIVISION IS REQUIRED ONLY IF SCALING IS USED TO AVOID OVERFLOW.
-- NO SCALING WAS USED IN THIS PROJECT, SO THAT RESULTS OF MATLAB MATCHED WITH OURS
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity divide is
port (
data_in : in std_logic_vector(31 downto 0) ;
data_out : out std_logic_vector(31 downto 0) ) ;
end divide ;

architecture rtl of divide is
begin
process(data_in)
variable divide_exp : std_logic_vector(7 downto 0) ;
variable divide_mant : std_logic_vector(31 downto 0) ;
begin
if (data_in = "00000000000000000000000000000000") then
data_out <= "00000000000000000000000000000000" ;
elsif (data_in = "10000000000000000000000000000000") then
data_out <= "00000000000000000000000000000000" ;
else
divide_exp := data_in(30 downto 23) ;
divide_mant := data_in (31 downto 0) ;
divide_exp := divide_exp - "00000001" ;
--data_out <= divide_mant(31) & divide_exp(7 downto 0) & divide_mant(22 downto 0) ;
data_out <= data_in(31 downto 0) ; -- pass data unchanged
end if ;
end process ;
end rtl ;
-- IO ADDRESS GENERATOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity ioadd_gen is
port (
io_butterfly : in std_logic_vector(3 downto 0) ;
add_iomode , add_ip , add_op : in std_logic ;
base_ioadd : out std_logic_vector(3 downto 0) ) ;
end ioadd_gen ;

architecture rtl of ioadd_gen is
begin
process(io_butterfly , add_iomode , add_ip , add_op)
variable out_data : std_logic_vector(3 downto 0) ;
begin
if(add_iomode = '1') then
if (add_ip = '1') then
out_data := io_butterfly(3 downto 0) ;
elsif(add_op = '1') then
if(io_butterfly(3) = '0') then -- ie, real part
out_data := '0' & io_butterfly(0) & io_butterfly(1) & io_butterfly(2) ;
elsif(io_butterfly(3)='1') then -- ie, complex part
out_data := '1' & io_butterfly(0) & io_butterfly(1) & io_butterfly(2) ;
end if ;
end if ;
end if ;
base_ioadd <= out_data(3 downto 0) ;
end process ;
end rtl ;

-- THIS FILE OUTPUTS THE "IO DONE" AND "STAGE DONE" AND "FFT DONE" SIGNALS AT THE
-- CORRECT TIME. IT ALSO RECEIVES THE OUTPUT OF THE BUTTERFLY GENERATOR
-- AND OUTPUTS IT UNCHANGED.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity iod_staged is
port (
but_fly : in std_logic_vector(3 downto 0) ;
stage_no : in std_logic_vector(1 downto 0) ;
add_incr , io_mode : in std_logic ;
add_iod , add_staged , add_fftd : out std_logic ;
butterfly_iod : out std_logic_vector(3 downto 0) ) ;
end iod_staged ;

architecture rtl of iod_staged is
begin
process(but_fly,add_incr,io_mode)
begin
if(but_fly = 15 and io_mode = '1' and add_incr='0') then
add_iod <= '1' ; -- io done signal
butterfly_iod <= but_fly ;
elsif(but_fly = 4 and io_mode = '0' and add_incr='1') then
butterfly_iod <= but_fly ;
add_iod <= '0' ;
add_staged <= '1' ; -- stage done signal
else
butterfly_iod <= but_fly ;
add_staged <= '0' ;
end if ;
end process ;

process(stage_no)
begin
if (stage_no=3) then
add_fftd <= '1' ; -- fft done signal
end if ;
end process ;

end rtl;
-- POSITIVE LEVEL TRIGGERED FLIP FLOPS
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity l_block is
port (
data_l : in std_logic_vector(31 downto 0) ;
trigger_l : in std_logic ;
l_out : out std_logic_vector(31 downto 0) ) ;
end l_block ;

architecture rtl of l_block is
begin
process(data_l , trigger_l)
begin
if (trigger_l='1') then
l_out <= data_l ;
end if ;
end process ;
end rtl ;
-- MULTIPLEXER TO CHOOSE BETWEEN CLOCK AND C0
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity mult_clock is
port (
clock_main , mult1_c0 , mult1_iomode , mult_clear : in std_logic ;
mult1_addincr : out std_logic ) ;
end mult_clock ;

architecture rtl of mult_clock is
begin
process(clock_main , mult1_c0 , mult1_iomode , mult_clear)
variable temp1 : std_logic ;
variable temp2 : std_logic ;
begin
if(mult1_iomode = '0') then -- ie, fft computation mode
temp2 := mult1_c0 ;
elsif(mult1_iomode = '1') then -- ie, io mode
temp1 := clock_main ;
end if ;
if (mult1_iomode = '1') then
mult1_addincr <= temp1 ;
elsif(mult1_iomode = '0') then
mult1_addincr <= temp2 ;
end if ;
end process ;
end rtl ;
-- MULTIPLY UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity multiply is
port(
num_mux , num_rom : in std_logic_vector(31 downto 0) ;
clock : in std_logic ;
mult_out : out std_logic_vector(31 downto 0) ) ;
end multiply ;

architecture rtl of multiply is
begin
process(num_mux , num_rom , clock)
variable sign_mult , t : std_logic := '0' ;
variable temp1 , temp2 : std_logic_vector(22 downto 0) ;
variable exp_mux , exp_rom : std_logic_vector(7 downto 0) ;
variable mant_temp : std_logic_vector(45 downto 0) ;
variable exp_mult , mux_temp , rom_temp : std_logic_vector(8 downto 0) ;
variable res_temp : std_logic_vector(31 downto 0) ;
begin

temp1 := '1' & num_mux(22 downto 1) ; -- '1' for implicit '1'.
temp2 := '1' & num_rom(22 downto 1) ;
if (num_mux(31) = '1' and num_rom(31) = '1' and clock = '1') then -- sign of results
sign_mult := '0' ;
elsif (num_mux(31) = '0' and num_rom(31) = '0' and clock = '1') then
sign_mult := '0' ;
elsif(clock = '1') then
sign_mult := '1' ;
end if ;

if (num_mux = 0 and clock = '1') then -- ie, the number is zero.
t := '1' ;
elsif (num_rom = 0 and clock = '1') then
t := '1' ;
elsif (clock = '1') then
t := '0' ;
end if ;

if (t = '0' and clock = '1') then -- separation of mantissa and exponent
exp_mux := num_mux (30 downto 23) ;
exp_rom := num_rom (30 downto 23) ;
mux_temp := '0' & exp_mux(7 downto 0) ;
rom_temp := '0' & exp_rom(7 downto 0) ;
exp_mult := mux_temp + rom_temp ;
exp_mult := exp_mult - 127 ;

mant_temp := temp1 * temp2 ;

if(mant_temp(45) = '1') then -- normalisation.
exp_mult := exp_mult + 1 ;
res_temp := sign_mult & exp_mult(7 downto 0) & mant_temp(44 downto 22) ;
mult_out <= res_temp(31 downto 0) ;
elsif(mant_temp(45) = '0') then
res_temp := sign_mult & exp_mult(7 downto 0) & mant_temp(43 downto 21) ;
mult_out <= res_temp(31 downto 0) ;
end if ;
elsif (t = '1' and clock = '1') then -- number zero
mult_out <= "00000000000000000000000000000000" ;
t := '0' ;
end if ;
end process ;
end rtl ;
-- multiplexer in the address generation unit
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity mux_add is
port (
a , b : in std_logic_vector(3 downto 0) ;
sel : in std_logic ;
q : out std_logic_vector(3 downto 0) ) ;
end mux_add ;

architecture rtl of mux_add is
begin
process (a , b , sel)
begin
if(sel = '0') then
q <= a(3 downto 0) after 2 ns ;
elsif(sel = '1') then
q <= b(3 downto 0) after 2 ns ;
end if ;
end process ;
end rtl ;
-- MULTIPLEXER IN THE BUTTERFLY PROCESSING UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity mux is
port (
d0 , d1 : in std_logic_vector(31 downto 0) ;
mux_out : out std_logic_vector(31 downto 0) ;
choose : in std_logic ) ;
end mux ;

architecture rtl of mux is
begin
process(d0 , d1 , choose)
begin
if (choose = '0') then
mux_out <= d0(31 downto 0) ;
elsif (choose = '1') then
mux_out <= d1(31 downto 0) ;
end if ;
end process ;
end rtl ;
--NEGATION UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity negate is
port (
neg_in : in std_logic_vector(31 downto 0) ;
neg_en , clock_main : in std_logic ;
neg_out : out std_logic_vector(31 downto 0) ) ;
end negate ;

architecture rtl of negate is
begin
process(neg_in , neg_en , clock_main)
variable neg_temp : std_logic_vector(31 downto 0) ;
begin
neg_temp := neg_in(31 downto 0) ;
if (clock_main = '1') then
if (neg_en = '1') then
if(neg_in(31) = '0') then
neg_temp := '1' & neg_temp (30 downto 0) ;
else
neg_temp := '0' & neg_temp (30 downto 0) ;
end if ;
neg_out <= neg_temp ;
else
neg_out <= neg_in(31 downto 0) ;
end if ;
end if ;
end process ;
end rtl ;

--while not endfile(vector_file) loop
--for count in 1 to 16 loop
-- Behavioral description of dual-port SRAM with :
-- Active High write enable (WE)
-- Active High read enable (RE)
-- Rising clock edge (Clock)
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.butter_lib.all ;
entity reg_dpram is
port (
data_fft , data_io : in std_logic_vector (31 downto 0);
q : out std_logic_vector (31 downto 0);
clock , io_mode : in std_logic;
we , re : in std_logic;
waddress: in std_logic_vector (3 downto 0);
raddress: in std_logic_vector (3 downto 0));
end reg_dpram;
architecture behav of reg_dpram is
type MEM is array (0 to 15) of std_logic_vector(31 downto 0);
signal ramTmp : MEM;

begin

-- Write Functional Section
process (clock,waddress,we)
begin
if (clock='0') then
if (we = '1') then
if (io_mode = '0') then
ramTmp (conv_integer (waddress)) <= data_fft ;
elsif (io_mode = '1') then
ramTmp (conv_integer (waddress)) <= data_io ;
end if ;
end if ;
end if ;
end process ;

-- Read Functional Section
process (clock,raddress,re)
begin
if (clock='1') then
if (re = '1') then
q <= ramTmp(conv_integer (raddress)) ;
end if;
end if;
end process;
end behav;
-- PARALLE IN PARALLEL OUT SHIFTER IN THE ADDRESS GENERATION UNIT.
-- REQUIRED BECAUSE FFT IS COMPUTED ON DATA AND WRITTEN BACK INTO THE SAME
-- LOCATION AFTER 5 CYCLES. SO THE READ ADDRESS IS SHIFTED THROUGH 5 CYCLES
-- AND GIVEN AS WRITE ADDRESS.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity ram_shift is
port (
data_in : in std_logic_vector(3 downto 0) ;
clock_main : in std_logic ;
data_out : out std_logic_vector(3 downto 0) ) ;
end ram_shift ;

architecture rtl of ram_shift is
begin
process(clock_main , data_in)
begin
if (clock_main'event and clock_main = '0') then
data_out <= data_in(3 downto 0) ;
end if ;
end process ;
end rtl ;
-- NEGATIVE EDGE TRIGGERED FLIP FLOPS
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity r_block is
port (
data : in std_logic_vector(31 downto 0) ;
trigger : in std_logic ;
r_out : out std_logic_vector(31 downto 0) ) ;
end r_block ;

architecture rtl of r_block is
begin
process(data , trigger)
begin
if (trigger='0' and trigger'event) then
r_out <= data(31 downto 0) ;
end if ;
end process ;
end rtl ;
-- ROM TO STORE SINE AND COSINE VALUES
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity rom is
port (
clock , en_rom : in std_logic ;
romadd : in std_logic_vector(2 downto 0) ;
rom_data : out std_logic_vector(31 downto 0) ) ;
end rom ;

architecture rtl of rom is
begin
process(clock,en_rom)
begin
if(en_rom = '1') then
if(clock = '1') then
case romadd is
when "000" =>
rom_data <= "00111111100000000000000000000000" ;
when "001" =>
rom_data <= "00000000000000000000000000000000" ;
when "010" =>
rom_data <= "00111111001101010000010010000001" ;
when "011" =>
rom_data <= "00111111001101010000010010000001" ;
when "100" =>
rom_data <= "00000000000000000000000000000000" ;
when "101" =>
rom_data <= "00111111100000000000000000000000" ;
when "110" =>
rom_data <= "10111111001101010000010010000001" ;
when "111" =>
rom_data <= "00111111001101010000010010000001" ;
when others =>
rom_data <= "01000000000000000000000000000000" ;
end case ;
end if ;
end if ;
end process ;
end rtl ;
-- ADDRESS GENERATOR FOR ROM
library ieee ;
use ieee.std_logic_1164.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity romadd_gen is
port (
io_rom,c0,c1,c2,c3 : in std_logic ;
stage_rom : in std_logic_vector(1 downto 0) ;
butterfly_rom : in std_logic_vector(3 downto 0) ;
romadd : out std_logic_vector(2 downto 0) ;
romgen_en : in std_logic );
end romadd_gen ;

architecture rtl of romadd_gen is
begin
process(io_rom,c0,c1,c2,c3,stage_rom,butterfly_rom)
begin
if(romgen_en = '1') then
if(io_rom = '0') then
case stage_rom is

when "00" =>
if(c0='1' or c2='1') then
romadd <= "000" ;
elsif(c1='1' or c3='1') then
romadd <= "001" ;
end if ;

when "01" =>
if(butterfly_rom=0 or butterfly_rom=1) then
if(c0='1' or c2='1') then
romadd <= "000" ;
elsif(c1='1' or c3='1') then
romadd <= "001" ;
end if ;
elsif(butterfly_rom=2 or butterfly_rom=3) then
if(c0='1' or c2='1') then
romadd <= "100" ;
elsif(c1='1' or c3='1') then
romadd <= "101" ;
end if ;
end if ;

when "10" =>
if(butterfly_rom=0) then
if(c0='1' or c2='1') then
romadd <= "000" ;
elsif(c1='1' or c3='1') then
romadd <= "001" ;
end if ;
elsif(butterfly_rom=1) then
if(c0='1' or c2='1') then
romadd <= "100" ;
elsif(c1='1' or c3='1') then
romadd <= "101" ;
end if ;
elsif(butterfly_rom=2) then
if(c0='1' or c2='1') then
romadd <= "010" ;
elsif(c1='1' or c3='1') then
romadd <= "011" ;
end if ;
elsif (butterfly_rom=3) then
if(c0='1' or c2='1') then
romadd <= "110" ;
elsif(c1='1' or c3='1') then
romadd <= "111" ;
end if ;
end if ;

when others =>
romadd <= "000" ;

end case ;
end if ;
end if ;
end process ;
end rtl ;
-- SHIFT UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use work.butter_lib.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;

entity shift2 is
port (
sub_control : in std_logic_vector (8 downto 0) ;
c_in : in std_logic_vector (32 downto 0) ;
shift_out : out std_logic_vector (31 downto 0) ;
clock , shift_en , rst_shift : in std_logic ;
finish_out : out std_logic ) ;
end shift2 ;
architecture rtl of shift2 is
begin
process(clock)
variable sub_temp : std_logic_vector(7 downto 0) ;
variable temp2 , temp4 : std_logic_vector(31 downto 0) ;
variable temp3 , t : std_logic ;
begin
if(rst_shift='0') then
if(shift_en = '1') then
if(temp3 = '1') then
if(sub_control(8) = '1') then
sub_temp := sub_control (7 downto 0) ;
temp2 := '1' & c_in (31 downto 1) ; --'1' for implicit one
temp3 := '0' ;
end if ;
end if ;
end if ;
end if ;

if(rst_shift='0') then
if(shift_en = '1') then
if(t = '1') then
if (sub_control(8) = '1') then
if (conv_integer(sub_temp(7 downto 0)) = 0) then
shift_out <= temp2 ;
finish_out <= '1' ;
t := '0' ;
elsif ( clock = '1') then
temp2 := '0' & temp2 (31 downto 1) ;
sub_temp := sub_temp - "00000001" ;
end if ;
end if ;
end if ;
end if ;
elsif(rst_shift='1') then
temp3 := '1' ;
finish_out <= '0' ;
t := '1' ;
end if ;

end process ;
end rtl ;
-- SUBTRACTOR UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity subtractor is
port (
a : in std_logic_vector (31 downto 0) ;
b : in std_logic_vector (31 downto 0) ;
clock , rst_sub , sub_en : in std_logic ;
a_smaller , fin_sub , num_zero : out std_logic ;
zero_detect : out std_logic_vector(1 downto 0) ;
sub : out std_logic_vector (8 downto 0) ;
change : out std_logic ) ;
end subtractor ;

architecture rtl of subtractor is
begin
process (a , b , clock , rst_sub , sub_en)
variable temp ,c , d : std_logic_vector (7 downto 0) ;
variable e , f : std_logic_vector (22 downto 0) ;
begin
if (rst_sub = '0') then
c := a (30 downto 23) ;
d := b (30 downto 23) ;
e := a (22 downto 0) ;
f := b (22 downto 0) ;

if(sub_en = '1') then
if (clock = '1') then
if ((c=0)) then
zero_detect <= "01" ;
num_zero <= '1' ;

elsif ((d=0)) then
zero_detect <= "10" ;
num_zero <= '1' ;

elsif (c < d ) then
temp := d - c ;
a_smaller <= '1' ;
sub <= '1' & temp (7 downto 0) ;
fin_sub <= '1' ;
zero_detect <= "00" ;
num_zero <= '0' ;

elsif (d < c) then
temp := c - d ;
a_smaller <= '0' ;
sub <= '1' & temp (7 downto 0) ;
fin_sub <= '1' ;
zero_detect <= "00" ;
num_zero <= '0' ;

elsif((c=d) and e < f) then
a_smaller <= '1' ;
temp:= c-d ;
sub <= '1' & temp (7 downto 0) ;
fin_sub <= '1' ;
zero_detect <= "00" ;
num_zero <= '0' ;

elsif ((c=d) and e > f) then
a_smaller <= '0' ;
temp := c-d ;
sub <= '1' & temp (7 downto 0) ;
zero_detect <= "00" ;
num_zero <= '0' ;
fin_sub <= '1' ;

elsif ((c=d) and (e = f)) then
temp := c-d ;
a_smaller <= '0' ;
sub <= '1' & "00000000" ;
fin_sub <= '1' ;
zero_detect <= "00" ;
num_zero <= '0' ;

end if ;
end if ;
end if ;

elsif(rst_sub = '1') then
fin_sub <= '0' ;
sub <= "000000000" ;
num_zero <= '0' ;
zero_detect <= "00" ;

end if ;

end process ;

process(a , b) -- process to identify when a new number comes
begin
change <= transport '1' after 1 ns ;
change <= transport '0' after 5 ns ;
end process ;

end rtl ;
-- SUMMER
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity summer is
port (
num1 , num2 : in std_logic_vector (31 downto 0) ;
exp : in std_logic_vector (7 downto 0) ;
addpulse_in , addsub , rst_sum : in std_logic ;
add_finish : out std_logic ;
sumout : out std_logic_vector ( 32 downto 0) ) ;
end summer ;
architecture rtl of summer is
begin
process (num1 , num2 , addpulse_in , rst_sum)
variable temp_num1 , temp_sum , temp_num2 , temp_sum2 , res : std_logic_vector (32 downto 0);
variable temp_exp : std_logic_vector (7 downto 0) ;
begin
if (rst_sum = '0') then
if (addpulse_in = '1') then
temp_num1 := '0' & num1 (31 downto 0) ; --0 to find whether normalisation is required.
temp_num2 := '0' & num2 (31 downto 0) ; --if required MSB will be 1 after addition

if (addsub = '1') then
temp_sum := temp_num1 + temp_num2 ;
sumout <= temp_sum ;
add_finish <= '1' ;

else
temp_sum := temp_num2 - temp_num1 ;
--res := temp_sum + temp_num1 ;
sumout <= temp_sum ;
add_finish <= '1' ;
end if ;
end if ;

elsif (rst_sum = '1') then
add_finish <= '0';
end if ;
end process ;

end rtl ;
-- SWAP UNIT
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity swap is
port (
a : in std_logic_vector (31 downto 0) ;
b : in std_logic_vector (31 downto 0) ;
clock : in std_logic ;
rst_swap , en_swap : in std_logic ;
finish_swap : out std_logic ;
d : out std_logic_vector (31 downto 0) ;
large_exp : out std_logic_vector (7 downto 0) ;
c : out std_logic_vector (32 downto 0 ) ) ;
end swap ;

architecture rtl of swap is
begin
process (a , b , clock , rst_swap , en_swap)
variable x , y : std_logic_vector (7 downto 0) ;
variable p , q : std_logic_vector (22 downto 0) ;
begin
if(rst_swap = '1' ) then
c <= '0' & a(22 downto 0) & "000000000" ;
finish_swap <= '0' ;
elsif(rst_swap = '0') then
if(en_swap = '1') then
x := a (30 downto 23) ;
y := b (30 downto 23) ;
p := a (22 downto 0) ;
q := b (22 downto 0) ;
if (clock = '1') then
if (x < y) then
c <= '1' & a (22 downto 0) & "000000000" ; -- '1' for checking
d <= '1' & b (22 downto 0) & "00000000" ; -- '1' for implicit one
large_exp <= b (30 downto 23) ;
finish_swap <= '1' ;

elsif (y < x) then
c <= '1' & b (22 downto 0) & "000000000" ;
d <= '1' & a (22 downto 0) & "00000000" ; -- '1' for implicit 1.
large_exp <= a (30 downto 23) ;
finish_swap <= '1' ;

elsif ( (x=y) and (p < q)) then
c <= '1' & a (22 downto 0) & "000000000" ; -- '1' for checking
d <= '1' & b (22 downto 0) & "00000000" ; -- '1' for implicit one
large_exp <= b (30 downto 23) ;
finish_swap <= '1' ;

else
c <= '1' & b (22 downto 0) & "000000000" ;
d <= '1' & a (22 downto 0) & "00000000" ; -- '1' for implicit 1.
large_exp <= a (30 downto 23) ;
finish_swap <= '1' ;

end if ;
end if ;
end if ;
end if ;
end process;
end rtl;

-- STAGE NUMBER GENERATOR.
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity stage_gen is
port (
add_staged , add_clear : in std_logic ;
st_stage : out std_logic_vector(1 downto 0) ) ;
end stage_gen ;

architecture rtl of stage_gen is

variable s_count : std_logic_vector(1 downto 0) ;
begin
process(add_staged , add_clear)
begin
if (add_clear = '1') then
st_stage <= "00" ;
s_count := "00" ;
elsif(add_staged'event and add_staged= '1' ) then
st_stage <= s_count + 1 ;
s_count := s_count + 1 ;
end if ;
end process ;
end rtl ;

--WAVEFORM GENERATOR
-- THE 4 BITS OF "DATA_OUT" ARE "C0 C1 C2 C3"
library ieee ;
use ieee.std_logic_1164.all ;
use work.butter_lib.all ;

entity cycles is
port (
clock_main , preset , c0_en , cycles_clear : in std_logic ;
waves : out std_logic_vector(3 downto 0) ) ;
end cycles ;
architecture rtl of cycles is
--type state_values is (st0 , st1 , st2 , st3) ;
--signal pres_state1 , next_state1 : state_values ;
shared variable data_out : std_logic_vector(3 downto 0) ;
begin
process (clock_main , preset , c0_en,cycles_clear)
variable t : std_logic ;
begin
if (c0_en = '1') then
if (preset = '1' and t='1')then
pres_state1 <= st0 ;
t := '0' ;
elsif (clock_main'event and clock_main= '0') then
pres_state1 <= next_state1 ;
end if ;
end if ;
if(cycles_clear = '1') then
t := '1' ;
end if ;
end process ;

process(pres_state1 , c0_en , clock_main)
variable temp_clock : std_logic ;
begin

case pres_state1 is
when st0 =>
data_out := "1000" ;
next_state1 <= st1 ;

when st1 =>
data_out := "0100" ;
next_state1 <= st2 ;

when st2 =>
data_out := "0010" ;
next_state1 <= st3 ;

when st3 =>
data_out := "0001" ;
next_state1 <= st0 ;

when others =>
next_state1 <= st0 ;

end case ;

waves <= data_out ;

end process ;
end rtl ;

-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity cont_gen is
port (
con_staged , con_iod , con_fftd , con_init : in std_logic ;
con_ip , con_op , con_iomode , con_fft : out std_logic ;
con_enbw , con_enbor , c0_enable , con_preset : out std_logic ;
con_clear , disable : out std_logic ;
c0 , clock_main : in std_logic ;
en_rom , en_romgen , reset_counter : out std_logic ;
con_clkcount : in std_logic_vector(2 downto 0) ) ;
end cont_gen ;

architecture rtl of cont_gen is
type state is (rst1,rst2,rst3,rst4,rst5,rst6,rst7) ;
signal current_state , next_state : state ;
shared variable counter , temp2 : std_logic_vector(1 downto 0) := "00" ;
begin
process (current_state ,con_staged , con_iod , con_fftd , con_clkcount , c0)

begin
case current_state is
when rst1 =>
con_iomode <= '1' ; -- set mode to io.
con_ip <= '1' ; -- input mode
con_clear <= '1' ; -- clear all blocks
con_enbw <= '1' ; -- enable write to RAM
con_enbor <= '0' ; -- disable read
c0_enable <= '0' ; -- disable cycles unit
disable <= '1' ; -- disable counter
next_state <= rst2 ;

when rst2 =>
con_clear <= '0' ; -- bring clear signal back to zero
next_state <=rst3 ;

when rst3 =>
if(con_iod = '1') then
con_preset <= '1' ; -- reset cycles
reset_counter <= '1' ; -- reset counter
c0_enable <= '1' ; -- enable cycles
con_iomode <= '0' ; -- set io mode to '0'
con_fft <= '1' ; -- fft mode
en_rom <= '1' ; -- enable ROM
en_romgen <= '1' ; -- enable ROM address generator
con_clear <= '1' ; -- clear all blocks
con_enbw <= '0' ; -- disable write to RAM
con_enbor <= '1' ; -- enable read from ROM
disable <= '0' ; -- enable counter unit.
next_state <= rst4 ;
else
next_state <= rst3 ;
end if ;

when rst4 =>
con_preset <= '0' ; -- reset for cycles
reset_counter <= '0' ; -- reset for counter
con_clear <= '0' ; -- clear all signals
if (con_clkcount = 5) then -- check whether 4 or not
con_enbw <= '1' ; -- enable write to ROM
disable <= '1' ; -- disable counter
reset_counter <= '1' ; -- reset counter
next_state <= rst5 ;
else
next_state <= rst4 ;
end if ;

when rst5 =>

if (con_fftd = '1') then
disable <= '0' ; -- enable counter
reset_counter <= '0' ;
con_clear <= '1' ; -- clear butterfly generator
con_fft <= '0' ; -- disable fft address generator
if (con_clkcount = 4) then
disable <= '1';
con_enbw <= '0' ;
con_iomode <= '1' ;
con_op <= '1' ;
con_ip <= '0' ;
next_state <= rst6 ;
else
next_state <= rst5 ;
end if ;
else
next_state <= rst5 ;
end if ;

when rst6 =>
con_clear <= '0' ;
next_state <= rst7 ;

when rst7 =>
if(con_iod = '1') then
con_clear <= '1' ;
con_preset <= '1' ;
con_enbor <= '0';
else
next_state <= rst7 ;
end if ;

when others =>
next_state <= rst1 ;

end case ;
end process ;

process(clock_main , con_init)
begin
if(con_init = '1') then
current_state <= rst1 ;
elsif (clock_main'event and clock_main = '0') then
current_state <= next_state ;
end if ;
end process ;
end rtl ;
-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity cont_gen is
port (
con_staged , con_iod , con_fftd , con_init : in std_logic ;
con_ip , con_op , con_iomode , con_fft : out std_logic ;
con_enbw , con_enbor , c0_enable , con_preset : out std_logic ;
con_clear , disable : out std_logic ;
c0 , clock_main : in std_logic ;
en_rom , en_romgen , reset_counter : out std_logic ;
con_clkcount : in std_logic_vector(2 downto 0) ) ;
end cont_gen ;

architecture rtl of cont_gen is
type state is (rst1,rst2,rst3,rst4,rst5,rst6,rst7) ;
signal current_state , next_state : state ;
shared variable counter , temp2 : std_logic_vector(1 downto 0) := "00" ;
begin
process (current_state ,con_staged , con_iod , con_fftd , con_clkcount , c0)

begin
case current_state is
when rst1 =>
con_iomode <= '1' ; -- set mode to io.
con_ip <= '1' ; -- input mode
con_clear <= '1' ; -- clear all blocks
con_enbw <= '1' ; -- enable write to RAM
con_enbor <= '0' ; -- disable read
c0_enable <= '0' ; -- disable cycles unit
disable <= '1' ; -- disable counter
next_state <= rst2 ;

when rst2 =>
con_clear <= '0' ; -- bring clear signal back to zero
next_state <=rst3 ;

when rst3 =>
if(con_iod = '1') then
con_preset <= '1' ; -- reset cycles
reset_counter <= '1' ; -- reset counter
c0_enable <= '1' ; -- enable cycles
con_iomode <= '0' ; -- set io mode to '0'
con_fft <= '1' ; -- fft mode
en_rom <= '1' ; -- enable ROM
en_romgen <= '1' ; -- enable ROM address generator
con_clear <= '1' ; -- clear all blocks
con_enbw <= '0' ; -- disable write to RAM
con_enbor <= '1' ; -- enable read from ROM
disable <= '0' ; -- enable counter unit.
next_state <= rst4 ;
else
next_state <= rst3 ;
end if ;

when rst4 =>
con_preset <= '0' ; -- reset for cycles
reset_counter <= '0' ; -- reset for counter
con_clear <= '0' ; -- clear all signals
if (con_clkcount = 5) then -- check whether 4 or not
con_enbw <= '1' ; -- enable write to ROM
disable <= '1' ; -- disable counter
reset_counter <= '1' ; -- reset counter
next_state <= rst5 ;
else
next_state <= rst4 ;
end if ;

when rst5 =>

if (con_fftd = '1') then
disable <= '0' ; -- enable counter
reset_counter <= '0' ;
con_clear <= '1' ; -- clear butterfly generator
con_fft <= '0' ; -- disable fft address generator
if (con_clkcount = 4) then
disable <= '1';
con_enbw <= '0' ;
con_iomode <= '1' ;
con_op <= '1' ;
con_ip <= '0' ;
next_state <= rst6 ;
else
next_state <= rst5 ;
end if ;
else
next_state <= rst5 ;
end if ;

when rst6 =>
con_clear <= '0' ;
next_state <= rst7 ;

when rst7 =>
if(con_iod = '1') then
con_clear <= '1' ;
con_preset <= '1' ;
con_enbor <= '0';
else
next_state <= rst7 ;
end if ;

when others =>
next_state <= rst1 ;

end case ;
end process ;

process(clock_main , con_init)
begin
if(con_init = '1') then
current_state <= rst1 ;
elsif (clock_main'event and clock_main = '0') then
current_state <= next_state ;
end if ;
end process ;
end rtl ;
-- CONTROL UNIT OF THE PROCESSOR
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity cont_gen is
port (
con_staged , con_iod , con_fftd , con_init : in std_logic ;
con_ip , con_op , con_iomode , con_fft : out std_logic ;
con_enbw , con_enbor , c0_enable , con_preset : out std_logic ;
con_clear , disable : out std_logic ;
c0 , clock_main : in std_logic ;
en_rom , en_romgen , reset_counter : out std_logic ;
con_clkcount : in std_logic_vector(2 downto 0) ) ;
end cont_gen ;

architecture rtl of cont_gen is
type state is (rst1,rst2,rst3,rst4,rst5,rst6,rst7) ;
signal current_state , next_state : state ;
shared variable counter , temp2 : std_logic_vector(1 downto 0) := "00" ;
begin
process (current_state ,con_staged , con_iod , con_fftd , con_clkcount , c0)

begin
case current_state is
when rst1 =>
con_iomode <= '1' ; -- set mode to io.
con_ip <= '1' ; -- input mode
con_clear <= '1' ; -- clear all blocks
con_enbw <= '1' ; -- enable write to RAM
con_enbor <= '0' ; -- disable read
c0_enable <= '0' ; -- disable cycles unit
disable <= '1' ; -- disable counter
next_state <= rst2 ;

when rst2 =>
con_clear <= '0' ; -- bring clear signal back to zero
next_state <=rst3 ;

when rst3 =>
if(con_iod = '1') then
con_preset <= '1' ; -- reset cycles
reset_counter <= '1' ; -- reset counter
c0_enable <= '1' ; -- enable cycles
con_iomode <= '0' ; -- set io mode to '0'
con_fft <= '1' ; -- fft mode
en_rom <= '1' ; -- enable ROM
en_romgen <= '1' ; -- enable ROM address generator
con_clear <= '1' ; -- clear all blocks
con_enbw <= '0' ; -- disable write to RAM
con_enbor <= '1' ; -- enable read from ROM
disable <= '0' ; -- enable counter unit.
next_state <= rst4 ;
else
next_state <= rst3 ;
end if ;

when rst4 =>
con_preset <= '0' ; -- reset for cycles
reset_counter <= '0' ; -- reset for counter
con_clear <= '0' ; -- clear all signals
if (con_clkcount = 5) then -- check whether 4 or not
con_enbw <= '1' ; -- enable write to ROM
disable <= '1' ; -- disable counter
reset_counter <= '1' ; -- reset counter
next_state <= rst5 ;
else
next_state <= rst4 ;
end if ;

when rst5 =>

if (con_fftd = '1') then
disable <= '0' ; -- enable counter
reset_counter <= '0' ;
con_clear <= '1' ; -- clear butterfly generator
con_fft <= '0' ; -- disable fft address generator
if (con_clkcount = 4) then
disable <= '1';
con_enbw <= '0' ;
con_iomode <= '1' ;
con_op <= '1' ;
con_ip <= '0' ;
next_state <= rst6 ;
else
next_state <= rst5 ;
end if ;
else
next_state <= rst5 ;
end if ;

when rst6 =>
con_clear <= '0' ;
next_state <= rst7 ;

when rst7 =>
if(con_iod = '1') then
con_clear <= '1' ;
con_preset <= '1' ;
con_enbor <= '0';
else
next_state <= rst7 ;
end if ;

when others =>
next_state <= rst1 ;

end case ;
end process ;

process(clock_main , con_init)
begin
if(con_init = '1') then
current_state <= rst1 ;
elsif (clock_main'event and clock_main = '0') then
current_state <= next_state ;
end if ;
end process ;
end rtl ;

-- OUTPUT RESULTS. SYNTHESISABLE
library ieee ;
use ieee.std_logic_1164.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity print_result is
port (clock,op : in std_logic ;
fin_res : out std_logic_vector(31 downto 0) ;
result : in std_logic_vector(31 downto 0));
end print_result ;

architecture rtl of print_result is
begin
process(op,clock)
variable count : integer := 1 ;
begin
if (op = '1') then
if (count < 17) then
if(clock='0' and clock'event) then
fin_res <= result ;
count := count + 1 ;
end if ;
end if ;
end if ;
end process ;
end rtl ;

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use work.butter_lib.all ;
use ieee.std_logic_unsigned.all ;

entity synth_main is
port (
data_io : in std_logic_vector(31 downto 0);
final_op : out std_logic_vector(31 downto 0) ;
clock_main,clock,enbl,reset,init : in std_logic) ;
end synth_main ;

architecture rtl of synth_main is
signal shft , waves : std_logic_vector(3 downto 0) ;

component subtractor
port (
a : in std_logic_vector (31 downto 0) ;
b : in std_logic_vector (31 downto 0) ;
clock , rst_sub , sub_en : in std_logic ;
a_smaller , fin_sub , num_zero : out std_logic ;
zero_detect : out std_logic_vector(1 downto 0) ;
sub : out std_logic_vector (8 downto 0);
change : out std_logic ) ;
end component ;

component swap
port (
a : in std_logic_vector (31 downto 0) ;
b : in std_logic_vector (31 downto 0) ;
clock : in std_logic ;
rst_swap , en_swap : in std_logic ;
finish_swap : out std_logic ;
d : out std_logic_vector (31 downto 0) ;
large_exp : out std_logic_vector (7 downto 0) ;
c : out std_logic_vector (32 downto 0 ) ) ;
end component ;

component shift2
port (
sub_control : in std_logic_vector (8 downto 0) ;
c_in : in std_logic_vector (32 downto 0) ;
shift_out : out std_logic_vector (31 downto 0) ;
clock , shift_en , rst_shift : in std_logic ;
finish_out : out std_logic ) ;
end component ;

component control_main
port (
a_small , sign_a , sign_b : in std_logic ;
sign_out , add_sub , reset_all : out std_logic ;
en_sub , en_swap , en_shift , addpulse , normalise : out std_logic ;
fin_sub , fin_swap , finish_shift , add_finish , end_all : in std_logic ;
clock_main , clock , reset , enbl , zero_num , change : in std_logic ) ;
end component ;

component summer
port (
num1 , num2 : in std_logic_vector (31 downto 0) ;
exp : in std_logic_vector (7 downto 0) ;
addpulse_in , addsub , rst_sum : in std_logic ;
add_finish : out std_logic ;
sumout : out std_logic_vector ( 32 downto 0) ) ;
end component ;

component normalize
port (
a , b : in std_logic_vector (31 downto 0) ;
numb : in std_logic_vector (32 downto 0) ;
exp : in std_logic_vector (7 downto 0) ;
signbit , addsub , clock , en_norm , rst_norm : in std_logic ;
zero_detect : in std_logic_vector(1 downto 0) ;
exit_n : out std_logic ;
normal_sum : out std_logic_vector (31 downto 0) ) ;
end component ;

component but_gen
port (
add_incr , add_clear , stagedone : in std_logic ;
but_butterfly : out std_logic_vector(3 downto 0) ) ;
end component ;

component stage_gen
port (
add_staged , add_clear : in std_logic ;
st_stage : out std_logic_vector(1 downto 0) ) ;
end component ;

component iod_staged
port (
but_fly : in std_logic_vector(3 downto 0) ;
stage_no : in std_logic_vector(1 downto 0) ;
add_incr , io_mode : in std_logic ;
add_iod , add_staged , add_fftd : out std_logic ;
butterfly_iod : out std_logic_vector(3 downto 0) ) ;
end component ;

component baseindex
port (
ind_butterfly : in std_logic_vector(3 downto 0) ;
ind_stage : in std_logic_vector(1 downto 0) ;
add_fft : in std_logic ;
fftadd_rd : out std_logic_vector(3 downto 0) ;
c0 , c1 , c2 , c3 : in std_logic ) ;
end component ;

component ioadd_gen
port (
io_butterfly : in std_logic_vector(3 downto 0) ;
add_iomode , add_ip , add_op : in std_logic ;
base_ioadd : out std_logic_vector(3 downto 0) ) ;
end component ;

component mux_add
port (
a , b : in std_logic_vector(3 downto 0) ;
sel : in std_logic ;
q : out std_logic_vector(3 downto 0) ) ;
end component ;

component ram_shift
port (
data_in : in std_logic_vector(3 downto 0) ;
clock_main : in std_logic ;
data_out : out std_logic_vector(3 downto 0) ) ;
end component ;

component cycles
port (
clock_main , preset , c0_en , cycles_clear : in std_logic ;
waves : out std_logic_vector(3 downto 0) ) ;
end component ;

component counter
port (
c : out std_logic_vector(2 downto 0) ;
disable , clock_main , reset : in std_logic) ;
end component ;

component mult_clock
port (
clock_main , mult1_c0 , mult1_iomode , mult_clear : in std_logic ;
mult1_addincr : out std_logic ) ;
end component ;

component cont_gen
port (
con_staged , con_iod , con_fftd , con_init : in std_logic ;
con_ip , con_op , con_iomode , con_fft : out std_logic ;
con_enbw , con_enbor , c0_enable , con_preset : out std_logic ;
con_clear , disable : out std_logic ;
c0 , clock_main : in std_logic ;
en_rom , en_romgen , reset_counter : out std_logic ;
con_clkcount : in std_logic_vector(2 downto 0) ) ;
end component ;

component and_gates
port (
waves_and : in std_logic_vector(3 downto 0) ;
clock_main , c0_en : in std_logic ;
c0,c1,c2,c3 : out std_logic ;
c0_c1,c2_c3,c0_c2,c1_c3 : out std_logic ) ;
end component ;

component r_block
port (
data : in std_logic_vector(31 downto 0) ;
trigger : in std_logic ;
r_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component l_block
port (
data_l : in std_logic_vector(31 downto 0) ;
trigger_l : in std_logic ;
l_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component level_edge
port (
data_edge : in std_logic_vector(31 downto 0) ;
trigger_edge : in std_logic ;
edge_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component mux
port (
d0 , d1 : in std_logic_vector(31 downto 0) ;
mux_out : out std_logic_vector(31 downto 0) ;
choose : in std_logic ) ;
end component ;

component negate
port (
neg_in : in std_logic_vector(31 downto 0) ;
neg_en , clock_main : in std_logic ;
neg_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component multiply
port(
num_mux , num_rom : in std_logic_vector(31 downto 0) ;
clock : in std_logic ;
mult_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component divide
port (
data_in : in std_logic_vector(31 downto 0) ;
data_out : out std_logic_vector(31 downto 0) ) ;
end component ;

component romadd_gen
port (
io_rom,c0,c1,c2,c3 : in std_logic ;
stage_rom : in std_logic_vector(1 downto 0) ;
butterfly_rom : in std_logic_vector(3 downto 0) ;
romadd : out std_logic_vector(2 downto 0) ;
romgen_en : in std_logic );
end component ;

component reg_dpram
port (
data_fft , data_io : in std_logic_vector (31 downto 0);
q : out std_logic_vector (31 downto 0);
clock , io_mode : in std_logic;
we , re : in std_logic;
waddress: in std_logic_vector (3 downto 0);
raddress: in std_logic_vector (3 downto 0));
end component ;

component rom
port (
clock , en_rom : in std_logic ;
romadd : in std_logic_vector(2 downto 0) ;
rom_data : out std_logic_vector(31 downto 0) ) ;
end component ;

component print_result
port (clock,op : in std_logic ;
fin_res : out std_logic_vector(31 downto 0) ;
result : in std_logic_vector(31 downto 0));
end component ;

begin

result : print_result port map (clock_main,op,final_op,ram_data) ;
but : but_gen port map (incr , clear , staged ,butterfly_iod) ;
stg : stage_gen port map (staged , clear , stage) ;
iod_stgd : iod_staged port map(butterfly_iod,stage,incr,io_mode,iod,staged,fftd,butterfly) ;
base : baseindex port map (butterfly , stage , fft_en , fftadd_rd , c0 , c1 , c2 , c3) ;
ioadd : ioadd_gen port map (butterfly , io_mode , ip , op , io_add) ;
ram_shift1 : ram_shift port map (fftadd_rd , clock_main , shift1) ;
ram_shift2 : ram_shift port map (shift1 , clock_main , shft) ;
ram_shift3 : ram_shift port map (shft , clock_main , shift3) ;
ram_shift4 : ram_shift port map (shift3 , clock_main ,shift4) ;
ram_shift5 : ram_shift port map (shift4 , clock_main , shift5) ;
--ram_shift6 : ram_shift port map (shift5 , clock_main , shift6) ;
multx1 : mux_add port map (shift5 , io_add , io_mode , ram_wr) ;
multx2 : mux_add port map (fftadd_rd , io_add , io_mode , ram_rd) ;
cyc : cycles port map (clock_main , preset , c0_en , cyc_clear , waves) ;
gates : and_gates port map(waves,clock_main,c0_en,c0,c1,c2,c3,c0_c1,c2_c3,c0_c2,c1_c3) ;
cnt : counter port map (clk_count , disable , clock_main , reset_count) ;
mux_clock : mult_clock port map (clock_main , c0 , io_mode , clear , incr) ;
control : cont_gen port map (staged , iod , fftd , init , ip , op , io_mode , fft_en ,
enbw , enbor , c0_en , preset , clear , disable , c0 , clock_main ,rom_en,romgen_en,reset_count,clk_count) ;

reg_ram : reg_dpram port map (out_data,data_io,ram_data,clock_main,io_mode,enbw,enbor,ram_wr,ram_rd) ;

f1 : r_block port map (ram_data , c0 , d2) ;
f2 : l_block port map (ram_data , c1 , d3) ;
f3 : r_block port map (ram_data , c2 , d4) ;
f4 : r_block port map (ram_data , c3 , d5) ;
f5 : r_block port map (d8 , c1_c3 , d9) ;
f6 : l_block port map (d8 , c0_c2 , d10) ;
f7 : l_block port map (d12 , c3 , d13) ;
f8 : l_block port map (d12 , c1 , d14) ;
f9 : r_block port map (d17 , clock_main , d18) ;
f10 : r_block port map (data_rom , clock_main , rom_ff) ;
mux1 : mux port map (d2 , d3 , d6 , c2_c3) ;
mux2 : mux port map (d4 , d5 , d7 , c1_c3) ;
mux3 : mux port map (d13 , d14 , d15 , c1_c3) ;
neg1 : negate port map (d10 , c0_c1 ,clock_main , d11) ;
neg2 : negate port map (d15 , c0_c1 ,clock_main , d16) ;
mult1 : multiply port map (d6 , rom_ff , clock_main , d8) ;
div : divide port map (d18 , d19) ;
f11 : level_edge port map (d19,clock_main,out_data) ;

rom_add1 : romadd_gen port map (io_mode,c0,c1,c2,c3,stage,butterfly,rom_add,romgen_en) ;
rom1 : rom port map (clock ,rom_en,rom_add,data_rom) ;

b11 : subtractor port map ( d16 , d7 , clock , rstb , ensubb , a_smallb , finsubb , numzerob , zerodetectb , subb , changeb) ;
b2 : swap port map ( a=>d16 , b=>d7 , clock=>clock , rst_swap=>rstb , en_swap=>enswapb , finish_swap=>finswapb , d=>swap_num2b , large_exp=>expb , c=>swap_num1b ) ;
b4 : shift2 port map (sub_control=>subb , c_in=>swap_num1b , shift_out=>shift_outb , clock=>clock , shift_en=>enshiftb,
rst_shift=>rstb , finish_out=>finshiftb ) ;
b5 : control_main port map ( a_smallb , d16(31) , d7(31) , signbitb , addsubb , rstb , ensubb ,
enswapb , enshiftb , addpulseb , normaliseb , finsubb , finswapb , finshiftb ,finish_sumb , end_allb ,
clock_main , clock , reset , enbl , numzerob , changeb ) ;
b6 : summer port map ( shift_outb , swap_num2b , expb , addpulseb , addsubb , rstb , finish_sumb , sum_outb ) ;
b7 : normalize port map (d16 , d7 , sum_outb , expb , signbitb , addsubb , clock , normaliseb , rstb , zerodetectb , end_allb , d17) ;

a1 : subtractor port map ( d9 , d11 , clock , rst , ensub , a_small , finsub , numzero , zerodetect , suba , changea) ;
a2 : swap port map (d9 ,d11 ,clock ,rst ,enswap , finswap ,swap_num2 , exp , swap_num1 ) ;
a4 : shift2 port map (suba ,swap_num1 ,shift_outa ,clock , enshift , rst , finshift ) ;
a5 : control_main port map ( a_small , d9(31) , d11(31) , signbit , addsub , rst , ensub ,
enswap , enshift , addpulse , normalise , finsub , finswap , finshift ,finish_sum , end_all ,
clock_main , clock , reset , enbl , numzero , changea ) ;
a6 : summer port map ( shift_outa , swap_num2 , exp , addpulse , addsub , rst , finish_sum , sum_out ) ;
a7 : normalize port map (d9 , d11 , sum_out , exp , signbit , addsub , clock , normalise , rst , zerodetect , end_all , d12) ;

end rtl ;

Prolog Symbolic Calc

Cy137 — Wed, 04 Nov 2009 13:40:32 GMT

I'm trying to write a program in prolog to do symbolic calculus. It's failing on several functions, of which I dont have the *exact* form of the input. These are:

Differentiation: Failed: [y_const, const_exp]

Integration: Failed: [multi_x, distributive, trig2, trig, const, simple_poly]

Any help?

is_var(x).

is_var(y).



is_constant(a).

is_constant(b).

is_constant(c).

is_constant(e).

is_constant(pi).

is_constant(X) :- number(X).



d(X,X,1) :- !.

d(Y,_,0) :- is_constant(Y),!.

d(Y,_,0) :- is_var(Y),!. % up to this clause, X != Y



% free_of(E,X) <=> expression E is free of X

free_of(X,X) :- !,fail.

free_of(Y,X) :- is_var(Y).

free_of(E,_) :- is_constant(E).

free_of(add(A,B),X) :- free_of(A,X), free_of(B,X).

free_of(sub(A,B),X) :- free_of(A,X), free_of(B,X).

free_of(mul(A,B),X) :- free_of(A,X), free_of(B,X).

free_of(div(A,B),X) :- free_of(A,X), free_of(B,X).

free_of(exp(A,B),X) :- free_of(A,X), free_of(B,X).

free_of(ln(A),X) :- free_of(A,X).

free_of(sin(A),X) :- free_of(A,X).

free_of(cos(A),X) :- free_of(A,X).



% canonicalize(E,X,R) <=> R is a canonical representation of E, mainly for terms of polynomials

%   For the canonicalized expression, constants appear first, and powers of x are grouped together,

%   making it appear as K*exp(X,M), where both K and M are free of X, note that K may be 1, and M may be 1 or 0



% assuming two canonicalized expressions, combining them into one canonicalized expression

canonicalize_combine(mul(mul(A,exp(X,M)),mul(B,exp(X,N))), X, mul(mul(A,B),exp(X,add(M,N)))) :- free_of(A,X), free_of(B,X).

canonicalize_combine(div(mul(A,exp(X,M)),nul(B,exp(X,N))), X, mul(div(A,B),exp(X,sub(M,N)))) :- free_of(A,X), free_of(B,X).

canonicalize(X,X,mul(1,exp(X,1))).

canonicalize(K,X,mul(K,exp(X,0))) :- free_of(K,X).

canonicalize(exp(X,M),X, mul(1,exp(X,M))) :- free_of(M,X),!.

canonicalize(mul(U,V),X, R) :- canonicalize(U,X,A), canonicalize(V,X,B), canonicalize_combine(mul(A,B),X,R).

canonicalize(div(U,V),X, R) :- canonicalize(U,X,A), canonicalize(V,X,B), canonicalize_combine(div(A,B),X,R).



%%%%%%DIFFERENTIATION EQUATIONS%%%%%%%%%%%%

d(add(U,V),X,R):-d(U,X,A),d(V,X,B),R=add(A,B).

d(sub(U,V),X,R):-d(U,X,A),d(V,X,B),R=sub(A,B).

d(mul(C,U),X,R):-atomic(C),C\=X,d(U,X,A),R=mul(C,A),!.

d(mul(U,V),X,R):-d(U,X,A),d(V,X,B),R=add(mul(U,B),mul(V,A)).

d(div(U,V),X,R):-d(U,X,A),d(V,X,B),R=div(sub(mul(A,V),mul(B,U)),exp(V,2)).

d(exp(U,C),X,R):-atomic(C),C\=X,d(U,X,A),R=mul(C,mul(A,exp(U,sub(C,1)))).

d(sin(W),X,R):-d(W,X,Z),R=mul(Z,cos(W)).

d(ln(W),X,R):-d(W,X,Z),R=div(Z,W).

d(cos(W),X,R):-d(W,X,Z),R=(mul(Z,-sin(W))).

d(exp(C,X),X,R):-atomic(C),C=E,d(W,X,Z),R=C*exp(W).



%%%%%%INTEGRATION EQUATIONS%%%%%%%%%%%%%%%%%%%%%%

in(A,X,R):-atomic(A),free_of(A,X),R=mul(A,X).

in(X,X,R):-R=div(exp(X,2),2).

in(exp(X,A),X,R):-atomic(A),R=div(exp(X,add(A,1)),add(A,1)).

in(div(C,X),X,R):-R=mul(C,ln(X)).

in(exp(e,X),X,R):-R=exp(e,X).

in(exp(A,X),X,R):-atomic(A),R=div(exp(A,X),ln(A)).

in(ln(X),X,R):-R=sub(mul(X,ln(X)),X).

in(sin(X),X,R):-R=(-cos(X)).

in(cos(X),X,R):-R=sin(X).

in(add(U,V),X,R):-in(U,X,A),in(V,X,B),R=add(A,B).

in(mul(add(U,V),W),X,R):-in(U,X,A),in(V,X,B),R=add(mul(W,A),mul(W,B)).

Tutorial or Reference for jacob?

Douglas Mokry — Tue, 03 Nov 2009 16:25:43 GMT

Does anyone know of a good place to find documentation for jacob?

MatLab, find area under experimental data plot

jakesee — Wed, 28 Oct 2009 15:58:29 GMT

Hi matlab experts,

I didn't think daniweb has a matlab forum so I went over to another math forum to ask for matlab help. but i think it's either I am too stupid for the mathematicians or they are too smart to realize that it is NOT obvious what i should do from just function and math theory names thrown at me... conclusion: daniweb explains the best =)

now, since there is no official matlab forum here, I hope I can just try my luck.

Question:
I have some experimental data points plotted y against t where t = 0 to 30, 0.5 interval. I want to find area under graph from, say, t = 0.832 to 5.672

How can I do it in matlab? Please show exact step by step as far as possible, because I am a matlab noob.

So far I have seen example from trapz and quads, but the also require the function f(t) to be known, which is not possible in my case because mine is experimental data.

I expect it to be something like this (psuedocode)

f = plot(t, y)

A = integrate(f, t1, t2)

matlab problem, help me experts plz

aabbddlah — Tue, 27 Oct 2009 20:59:58 GMT

Hello everyone

i v just joined the forum and i would like u to give me some sort of help in my induction motor project
i am using matlab to carry out the value for torque and then plot the torque Vs speed graph using matlab

so torque should be calculated for different speeds and slips
(Not only different values of speed!)
So
given the following parameters

R2=.8ohm
Rt=1.2ohm
Lt=2.2ohm
L2=3 ohm
v=225v
s = (ws-wr) / ws , where ws=synchronous speed and wr=rotor speed
i2= as in attachment

torque=(3./wr)*(I2^2)*(R2/s)*(1-s)

Also current cannot be one constant value
It should be calculated accordingly to slip values, so for each slip value we should have a value for current
To sum up , I think that we should use for loop to carry out values of slip ,corresponding speed ,and corresponding current on a range of values to create the proper plot
If the code is correct we must end up with the graph shown in the attachment
I will be thankful if u would help me
Many thanks

Attached Images

	a propper output1.jpg (8.9 KB)
	a worked ex.jpg (148.8 KB)

Pseudocode to Program

blackbetty76 — Sat, 24 Oct 2009 05:12:28 GMT

I am in a Prrogramming with Algoritims class, I have struggling a bit. We are working on a currency conversion table. Here is the assignment:

• Generate a set of test inputs and expected results for the Currency Conversion program.

Do I need to complete a program in order to know my test results? I'm really not sure what I need to do next, can anyone help?

Blackbetty76

Help With Scheme Procedure

vileoxidation — Thu, 22 Oct 2009 23:53:20 GMT

Hello, and thank you for taking the time to help me! I am working on a Scheme procedure right now, which is supposed to read in integers until 0 is entered, and display the minimum of the integers (0 included). I have a question about the procedure, which is below. Keep in mind, I have only written ONE Scheme procedure thus far, which displayed the minimum of two integers, so it was much easier. So here is my question:

In the header, what do I put for the conditions after lambda? How do I tell the procedure that it needs to read in ints until 0 is entered?

Thank you for any help you can provide!

MATLAB.. with Access?!!

Fadiy — Thu, 22 Oct 2009 20:31:51 GMT

Hi all...

well.. the thing is that me & my team are working on our graduating project

we are using MATLAB.. and we need to use a database
we've tried Access.. but it seems hard as we need to store images in the database

when we tried to retrieve the image in matlab, the only thing we saw was a bunch of numbers, which by my guess would be the pixels of the picture?

any one has an idea of the best database system to use with matlab? and how to retrieve images from the database to the matlab workspace?

thanx a lot ^_^

please help me write this prog in lisp

maddy1985 — Sat, 17 Oct 2009 03:24:56 GMT

a. create a list that stores the courses that you are taking this semester where the courses are stored in sublists as (designator number) such as (csc 375) so that your list will look like this: ((csc 375) (his 100) (cit 140) (csc 402) (eng 200)) and then create 3 other lists for fictitious CSC and/or CIT majors. All students except one should have at least one eng class. They should all have at least 2 courses, no more than 7.
b. write the following functions*
i. given a course list and a designator, print all courses of that designator
ii. given a course list, print all upper level courses (3xx and 4xx courses)
iii. given a course list, count the number of courses that are either CSC or CIT and returns that number
iv. given a course list, determine whether a given schedule is “hard”, “easy” or “in between” where a “hard” schedule is one where the student is taking only upper level courses, or only CIT/CSC courses, an easy schedule is one where the student is taking only 100 or 200 level courses or is one with no CSC or CIT courses, and in between is everything else, your function should return how hard the schedule is
c. run the four functions on your 4 student course lists, use ’eng as the designator when you try out the function from 5.b.i.

I am new to lisp so please help me...

Computer Networks question

imclumsy — Fri, 02 Oct 2009 04:35:28 GMT

Hi I am having trouble creating a pseudocode for this question, but I did give it a shot. I hope someone can help. This is the question.

Consider the concurrent logical channels protocol. This protocol does not guarantee that messages are delivered in order. Modify the protocol to ensure that this is the case. I suggest you always send messages in channel order (first over channel 0, then over channel 1, then over channel 2, etc up to n-1 and then back over to channel 0). Modify the receiver to deliver messages to the application also in channel order (first channel 0, then 1, etc.). Modify also the receiver to have one buffer space for each channel (in case messages arrive out of order)

this is the original pseudocode:

process sender

variables

body : data from higher layer

sb: bit of last frame sent

ab: bit of last acknowledgment

begin

when sb = ab then

body := message from higher layer

sb := (sb+1) mod 2

19

send frame(sb, body) to receiver

when receive ack(ab) then

skip

when timeout for last message sent then

if sb ≠ ab then

send frame(sb, body) to receiver

end



process receiver

variables

body : data to be delivered to higher layer

nb: bit of next frame to deliver to app

b: bit in frame just received

begin

when receive frame(b, body) then

20

send ack(b) to sender

if b = nb then

deliver body to higher layer

nb := (nb + 1) mod 2

this is my psedocode:



process sender



const   N : number of logical channels



 



variables



body :     array[0 .. N-1] of whatever



sb:           array[0 .. N-1] of 0 .. 1



ab:          array[0 .. N-1] of 0 .. 1



b:            0 .. 1 {bit in ack}



n:            0 .. N-1 {channel number in ack}



 



begin



   for any i, 0 ≤ i < N, //i is the channel number



                when sb[n] = ab[n] then



                                body[n+1] := message from higher layer       



                                sb[i] := (sb[i] + 1) mod 2



                                send frame(i, sb[n+1], body[n+1]) to receiver



   when receive ack(n, b) then



                                ab[n] := b



   for any i, 0 ≤ i < N,



                when timeout for message sent in channel i then



                                if sb[i] ≠ ab[i] then



                                                send frame(i, sb[i], body[i]) to receiver



end



 



process receiver



const    N:  number of channels



variables



nb:    array [0 .. N-1] of 0..1 {next bit expected}



body:  data to be delivered to higher layer



b:     0..1  {bit received in frame}



n:     0 .. N-1 {channel number of frame}



begin



when receive frame(n, b, body) then



                                if b = nb[n] then //if the received bit is the next bit expected then send ack



send ack(n, b) to sender



                                if b = nb[n] then



                                                deliver body to higher layer



                                                nb[n] := (nb[n] + 1) mod 2

Can someone help?

Thanks.

Help with FORTRAN

virtualmisc — Thu, 01 Oct 2009 21:34:29 GMT

Anyone here knows anything about FORTRAN.
Planning on doing a research on FORTRAN.
Help is really appreciated.

HEX dump

Dentkiller — Mon, 28 Sep 2009 05:09:45 GMT

Re: permutation of a string

haroonjamia — Sat, 26 Sep 2009 06:32:18 GMT

Quote:

Originally Posted by varunrathi (Post 72258)

Can anybody help me with permutation in c++. say if the entered string is "stop" then there must be 24 (=4*3*2*1) different words made by the letters s,t,o,p. Similarly if the entered string is "abcde" then there will be 120 (=5*4*3*2*1) different words made using the letters a,b,c,d,e.
Please Help. It`s eating up my head.

Dear Varunrathi
the problem you are asking to resolve is same as my problem.
Your mind is eaten up and i m totally eaten up by this problem, I am also looking
for some people who dared to solve this by programming. I work under ForTran,
so if you have got your problem resolved, can you pass me the algorithm to do
the permutation. my email id is SNIP
please, for god sake
Thank you

plz plz help me in LABVIEW

adeelghani — Fri, 25 Sep 2009 06:42:12 GMT

hello to every one

im making a GUI in labview and i want to take serial data in labview im new in labview so plz help me

thanks for replyng

need university help first year

umarmaqsood — Fri, 25 Sep 2009 05:32:06 GMT

hey this is umar here and i really needed some help because i have my exam tommorow. i was assigned to make a robot. ad to program it as some of may you know( i hope) the NXC language (i think its called that) to program the Mindstorms nxt brick. if some can help me i only have limited knowledge, i need to make this robot stay away from this color yellow and stay in black , i will be given a a small rink or arean painted black (as big as a air hockey table) and rest painted yellow. there will also be another robot that will try to catch my robot so i have to make my robot escape for about 90 secs. i have written some code if some of you can help that would be great.[description of my robot: its both sensors are on the front( light sensor facing ab to the ground and the distance one facing straight forwarf) the two motors are on the front wheels and one tire on the back. and here is my code so far.

#include "NXCDefs.h"



mutex moveMutex;

#define dist  60

#define extranear  10

int tries = 0;









inline void scan_front()

{

  

  SetSensorLowspeed(IN_1);

  







if (SensorUS(IN_1) > dist)

{



    OnFwd(OUT_AB, 75);

        tries = 0;

}        



if (SensorUS(IN_1) < dist){



Off(OUT_AB);

RotateMotor(OUT_A, 80, 300);

tries++;





}



if(SensorUS(IN_1) < extranear)



{

Off(OUT_AB);



RotateMotor(OUT_A, 80, 720);





}





if(tries >= 3 ){

Off(OUT_AB);

 OnFwd(OUT_AB, 75);

}









}













task main()

{

 



while (true){





scan_front();









}







}

*Update: the tries thing i did doesnt seem to work.

Error when using a contraint in Access

RenFromPenn — Tue, 22 Sep 2009 19:55:39 GMT

Hi,

I am trying to complete an example from the book SQL for Microsoft Access. I have typed it into Access just as it appears in the book. When I run it, however, I get an error message telling me that there is a "Syntax error in Constraint clause." I have checked and checked and I am fairly certain that I typed it in right. Anyway, here is the code from the book.

CREATE TABLE Manufacturers

(

ManufacturerID INTEGER CONSTRAINT ManfID PRIMARY KEY,

ToyID INTEGER NOT NULL,

CompanyName CHAR (50) NOT NULL,

Address CHAR (50) NOT NULL,

City CHAR (20) NOT NULL,

State CHAR (2) NOT NULL,

AreaCode CHAR (3) NOT NULL,

PhoneNumber CHAR (8) NOT NULL UNIQUE,

CONSTRAINT ToyFk FOREIGN KEY (ToyID) REFERENCES Toys (ToyID) 

ON UPDATE CASCADE 

ON DELETE CASCADE

);

Does Access 2007 support constraints? If so, then could you please offer a guess as to what the problem could be? Oh, and yes, I did previously create the Toys table, so it can't be generating an error because of that being missing.

Ren

VFP help

NEGATIVEQUITY — Wed, 16 Sep 2009 14:18:37 GMT

hey all, i've asked this on a number of VFP sites and gotten many different answers- can anyone tell me how to include programming in VFP7 to strip Windows line breaks-
hex:
0D 0A
which is Chr(13) and Char(10) which is a line break for Windows

any help is greatly appreciated

Automation of SAP transaction analysis

mainoffender — Wed, 16 Sep 2009 07:00:21 GMT

Hi everyone!
My name is Max and I’ve been an ABAP programmer for 6 years now. Since my work is closely connected with SAP I have to face the very same annoying problem pretty often. The thing is, sometimes it is vital important to know the base data model and an internal structure of SAP transactions which are typically very complex and are always developed in a messy manner. So even for a professional it is hard and so time-consuming to find lead essences act in transaction, its relations and key fields, enhancement and integration points etc.
So I start wondering if there is any kind of program, utility or application that might automate the process, completely or partially, and finally lighten things up.
Any ideas? Thanks in advance.
Sincerely, Max.

Learning a language online

insegnanteina — Mon, 14 Sep 2009 21:27:47 GMT

Learning a language online via skype or Messenger is the new tecnology, that provides you with all the knowledge and comfort of the XXI century. In the era of Iphone, laptop etc. even learning a language should be easy and less effortless.Share with me your opinions on the matter.

i do really need your help guys... its about mobile application in netbeans

xilamei — Thu, 10 Sep 2009 08:41:54 GMT

hi... i do really need your help guys... its about mobile application in netbeans IDE 6.7.1

im a total newbie here...

so, im asking for your help...

so here it goes, i am planning to create a mobile application with the use of netbeans IDE 6.7.1, and the outcome would be like a call/text message blocker...

what i want to happen is that when the mobile phone user enter a number on the application, it will automatically block any messages and/or calls from that number... please please please help me:(

thanks alot:)

scheme help, new to it

deltemis — Thu, 10 Sep 2009 05:11:44 GMT

hi all, trying to write a function nonlat? which returns true if the given list does not contain any atoms. so an empty list would be a nonlat and return true.

the tests i'm supposed to use are:

(nonlat? '(a b c))
(nonlat? '(a (b) (c)))
(nonlat? '((a b) ((c)) (d)))
(nonlat? '())

and the results are supposed to be #f, #f, #t and #t

i've managed to get this code but not sure how to get the third to turn out a #t instead of a #f. i've only gotten it down to this, pretty basic but a start

(define nonlat?
(lambda (list)
(null? list)))

second problem is to write a function member-cat? which returns true if the atom cat is a member of the given list, otherwise it returns false. it's also supposed to only take 1 argument which is the reason for the tests being like they are

the tests for this function is:
(member-cat? '())
(member-cat? '(bird cat dog))
(member-cat? '(hamster turtle))
(member-cat? '(cat))

and it should return #f, #t, #f, #t respectively. so far with the second function i've managed to get it to work for all but the second test, classmate says to use recursive call and hard code 'cat into it but not sure exactly how to do that

(define member-cat?
(lambda (lat)
(cond
((null? lat) #f)
(else (or (eq? 'cat (car lat)))))))

GW Basic variables

kanga85 — Fri, 04 Sep 2009 03:17:58 GMT

I have a program in GW Basic to collect data, and it needs to be re-written as the data is increasing and would be best handled within a loop.

I read in range of string data; "A", "B", .... within the loop. I then need to input, from the keyboard, numerical data, say A1, A2, A3, A4 against each of these String variables.

Q. How do I convert string "A" into numerical variables A1, A2, ...? I cannot find anyway in GW Basic that allows this.

Thanks

Foxpro application with timer

lasherz2 — Tue, 01 Sep 2009 18:30:08 GMT

We are using foxpro application as a bridge between two systems.Well,at midnight the bridge seems to drop the connection and hence theres no communication betwen the two systems.The network link seems pretty fine.The other issue is that the bridge does not change the date at midnight.This seems to happen every day.Any ideas as to what happens?

Good Language for Programming AI

h3llpunk — Sun, 30 Aug 2009 11:11:17 GMT

Hello,

I have an interest in AI and i would like to start learning a language thats really suited for AI.
I must say i only have some basics in programming, which language would be best suited for me to start doing some AI?.
And what are good tutorials to start with the language?

h3llpunk

Matlab problem

bufospro — Sun, 23 Aug 2009 11:54:01 GMT

Hi all,
I am mew in matlab and I have to read a text and then make a vector with the binary value of their chars.

For example :
text = 'pr'
ascii = 1010000
1110010

I want to make a vector like that -->
[1;0;1;0;0;0;0;1;1;1;0;0;1;0]

My code is

function bits_vector = textbin(text)



text_ascii = uint8(text);

num = length(text_ascii)



bits_matrix = dec2bin(text_ascii,7)-'0';



len_vector = num*8



bits_vector = zeros(len_vector,1)



for i=1:len_vector

    bits_vector(i:(i+7)) = bits_matrix(i,:)

    i=i+8;

end

Any help ? Please

Thank you

help create a 4 bit adder with one output using PLDs

STUDENT#101 — Tue, 18 Aug 2009 16:59:49 GMT

Hello I am a beginner in programming using PLDs and am trying to figure out how I could get all the sums and carries of the 4 bit adder to be outputed onto one pin.

One in ectual fact I am designing a PLD that can do both arithmetic and logical peration. and am stuck with this small problem.

Any input will be appreciated

Adding text to a TV tuner

janverge — Mon, 17 Aug 2009 07:55:36 GMT

Hello Deniweb readers,

May i ask if is it possible to put a text or a string message layer in a screen's tv tuner.

I am thinking of putting a message alert lets say a network with n numbers of Television connected to a PC with tv tuner. My task is to pop a message lets say by scheduling or manually and then clears everything when I want to. The thing is I should be able to control the message to show and as well gracefull enough to clear the message. The message may be in a transparent background with font, size ,color and coordinates customizable. It should also support gradient or opaque background within the text message.
Also, it should be light weight enought not to congest the network for I will also want to put a clock at the lower right corner and a scrolling marquee text message on the bottom..

Will this be possible? What would be the setup in C#.net?
Please advise.

Sincerely,
Jan

Sudoku Solver in Ruby

ClimaxBeetle — Sun, 16 Aug 2009 07:26:29 GMT

This is actually a quiz in our Algorithm Analysis and Design class where we're provided a 9x9 sudoku table filled with few numbers. Now, our teacher allowed us to use any programming language, provided that it's structural and not OOP, in order to come up with a sudoku solver app.

Here's the catch, the 9x9 sudoku grid has few numbers and the program should be able to fill in possible numbers to complete the grid.

I decided to start programming/coding it on ruby by making 9 arrays, assuming that they're the 9 rows.

Note that we have to provide the algorithm though.