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Memory interface Problem!!!
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1) Design a memory system with 4 MB ROM and 8 MB RAM. The system should use four
banks of 8-bit wide RAM and four banks of 8-bit wide ROM. ROM should start at address
0x00000000. ROM and RAM should be contiguous. Use partial address decoding. Be sure
to include the following:
· A truth table for the memory decoder.
· A listing of which address and data lines are connected to each RAM and ROM chip.
· The memory map for the system.
2) Determine the minimum address range that is required for a system consisting of 2 ARM
PrimeCell General Purpose I/O devices and one ARM PrimeCell UART.
Can someone help as to how to go about on this? I am quite confused overall...I don't need the full answers but some hints which might help me solving this! Thank you
banks of 8-bit wide RAM and four banks of 8-bit wide ROM. ROM should start at address
0x00000000. ROM and RAM should be contiguous. Use partial address decoding. Be sure
to include the following:
· A truth table for the memory decoder.
· A listing of which address and data lines are connected to each RAM and ROM chip.
· The memory map for the system.
2) Determine the minimum address range that is required for a system consisting of 2 ARM
PrimeCell General Purpose I/O devices and one ARM PrimeCell UART.
Can someone help as to how to go about on this? I am quite confused overall...I don't need the full answers but some hints which might help me solving this! Thank you
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