So, I'm studying Processor Design (very basic lol)
but I need some input..
In a 1-Bus architecture for a CPU, doing an operation at the same time like:
R[3] <- R[1] + R[2] : R[4] <- R[3] + R[1] + R[2];
where if R1 = 5; R2 = 6; R[3] = 5 (before first instruction);
after the two instructions are finished, R[3] = 11; and R[4] = 16
can be accomplished easily; however, for a 2 bus architecture is this possible?
I'm finding that it can't be, but I want some more input. Thanks for the help!
Here's a 1-Bus:
http://edu.cs.tut.fi/PD2009/figs/EPs_arith/src1bus.jpg
Here's a 2-Bus:
http://edu.cs.tut.fi/PD2009/figs/EPs_arith/src2bus.jpg
