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The acronym RISC (pronounced risk), for Reduced Instruction Set Computing represents a CPU design strategy emphasizing the imminent that basic instructions which "do less" may still offer for advanced performance if this simplicity can be utilized to make instructions perform very fast. This is basically supports High-Level Language simpler, rather than further complexity. This means the clock can run faster. The objective of a RISC processor is to execute one instruction on every clock cycle. A large number of general-purpose registers, or the use of compiler technology to optimize register usage this saves operand referencing. Identical general purpose registers, allowing any register to be used in any context, simplifying compiler design (although normally separate floating point registers).
There is only one bus to main memory, which is shared between instructions and data, but within the processor, the address and data are separated, which is termed a “Harvard Architecture”. By having separate instruction and data caches, both an instruction and also a datum can be fetched in a single clock cycle, enabling an instruction to be executed every cycle, even if that instruction also needs data. RISC processors aim to execute one instruction per clock cycle, therefore the ALU will perform operations in a single cycle. However, the ALU operation does not represent everything that needs to be done in order for an instruction to execute. The instruction needs to be fetched, decoded and then results need to be written back to main memory or the register file. However, the RISC strategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in more or less the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.
Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MULT" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place.
The main features of RISC
A limited and simple instruction set: These can be executed rapidly at high clock speeds by hardwired, pipelined performance.
Register oriented instructions, with very limited memory access: Only few basic LOAD and STORE instructions can access data in memory. All other instructions operate only with registers.
A fixed length, fixed format instruction word: Allows instructions to be fetched and decoded independently. No need to wait until the length of a previous instruction is known in order to fetch and decode the next instruction.
A large bank of registers: Variables and intermediate results do not require the use of memory. Thus many LOADs and STORES can be avoided.
There are Number of RISC processor architectures
MIPS
ARM
PowerPC
Hitachi SH
i960
The main RISC Architectures are MIPS and ARM. They are the companies that just define the architecture, leaving other companies to produce and sell processors. Both have several licensees manufacturing products. At the other end of the spectrum other architectures are available from only one vendor.
ARM — The ARM architecture dominates the marketplace for high performance, low power, low cost embedded systems (typically 100–500 MHz in 2008). ARM Ltd., which licenses intellectual property rather than manufacturing chips, reported 10 billion licensed chips shipped in early 2008. ARM is deployed in countless mobile devices such as:
• Apple iPods (custom ARM7TDMI SoC)
• Apple iPhone (Samsung ARM1176JZF)
• Palm and PocketPC PDAs and smartphones (Intel XScale family, Samsung SC32442 - ARM9)
• Nintendo Game Boy Advance (ARM7)
• Nintendo DS (ARM7, ARM9)
• Sony Network Walkman (Sony in-house ARM based chip)
• Some Nokia and Sony Ericsson mobile phones
MIPS's MIPS line, found in most SGI computers and the PlayStation, PlayStation 2, Nintendo 64 (terminated), PlayStation Portable game consoles, plus residential gateways like Linksys WRT54G series.
IBM's and Freescale's (formerly Motorola SPS) Power Architecture, used in all of IBM's supercomputers, midrange servers and workstations, in Apple's PowerPC-based Macintosh computers (terminated),), in Nintendo's Gamecube and Wii, Microsoft's Xbox 360 and Sony's PlayStation 3 game consoles, and in many embedded applications like printers and cars.
Sun's SPARC line, found in most of their later machines
Hewlett-Packard's PA-RISC, also known as HP/PA (terminated),
DEC Alpha, still used in some of HP's workstation and servers (terminated),
XAP processor used in much low-power wireless (Bluetooth, wifi) chips from CSR.
Hitachi's SuperH, originally in wide use in the Sega Super 32X, Saturn and Dreamcast, now at the heart of many consumer electronics devices. The SuperH is the base platform for the Mitsubishi - Hitachi joint semiconductor group. The two groups merged in 2002, dropping Mitsubishi's own RISC architecture, the M32R.
Atmel AVR used in a variety of products including ranging from Xbox hand controllers to BMW cars
Advantages of RISC
Advantages of reduced instruction set machine
Faster
Simple Hardware
Shorter Design cycle due to simpler hardware
Disadvantages of RISC
Drawbacks of a reduced instruction set computer include
Programmer must pay close attention to instruction scheduling so that the processor does not spend a large amount of time waiting for an instruction to execute
Debugging can be difficult due to the instruction scheduling require very fast memory systems to feed them instructions
Nearly all modern microprocessors including Pentium (hybrid RISC/CISC) Power PC, Alpha and SPARC microprocessors are superscalar
