I can't figure out how to get rid of this race condition I'm getting in my synthesizable verilog code. Basically, I'm generating an input value for a module, and at positive edge of my clock I capture that value at my module. The problem is that I want the value post-clock-rise and not pre-clock-rise. Has anyone had this problem before? It seems like it would be common... Any help you can give me would be great.
