It's always fun to root for the underdog. It's the American way to cheer for the little guy, hoping he'll triumph over the dark forces of--ironically enough--Corporate America. AMD has been squarely in the underdog role for quite awhile now, but the brewing Hammer v. Itanium match-up will take that to a whole new level.
IA-64 is a new VLIW design that has x86 compatibility tacked on; Hammer is a real x86 processor (albeit one with 64-bit extensions) just like Athlon, K6, and AMD's other processors before it. The two product lines are now heading down separate paths. You're always the winner when you run a race by yourself. But when you reach that finish line, are you anyplace you want to be?
In this second part of our three-part analysis on 64-bit computing architectures, we'll delve into Hammer's microarchitecture and compare/contrast to Itanium's existing design coming up design.
Hammer's external interfaces are as interesting as Itanium's are dull. First off, Hammer includes two double data-rate (DDR) controllers that directly manage external SDRAM memory. The memory bus can be either 64 bits or 128 bits wide, and requires no glue logic. This compares favorably to Itanium's generic (and short-lived) system bus, which requires a separate Intel controller chip to make sense of memory.
Sexier still, Hammer includes three (count 'em!) HyperTransport links, an obvious advantage over Itanium in multiprocessing. This bus is relatively open and has bandwidth to spare. Depending on how you arrange them, up to eight Hammer processors can seamlessly communicate amongst themselves using nothing but their built-in HyperTransport links. Anybody remember the Transputer? Whereas Itanium processors have to share a system bus, each Hammer gets its own private memory, courtesy of its on-chip SDRAM controller. (The first Hammer processor, Clawhammer, may only support two processors using a single HyperTransport link). :D
