Reading cache latency graph

[DarkLightning7]

I have this cache latency graph and I am trying to figure out how to find the cache block size for L1, L2 and L3 caches from it but I cant find anything on how to do so I was able to guess the total cache size though.

Any help is appreciated thanks.

[DarkLightning7]

I guess I should have clairified what the data points are. The left side is nanoseconds the bottom is the size of the step we are taking through memory and the right side is the size of chunks of memory we are dealing with. These chunks are simply integer arrays generated in c. The steps are how much of the array we are skipping over before reading another value.

[rubberman]

L1, L2, and L3 cache are hardware based. The cache block size is probably determined by the CPU (L1 and possibly L2), or system board BIOS/flash settings (L2 and/or L3). I don't think that the OS has much to do with that, though I may be wrong. The standard Linux memory block size is 4K (4096 bytes).

[DarkLightning7]

Thanks for the reply.
The cache block sizes for the cpu are fixed, "hard wired," and I believe the motherboard cache block sizes are as well, Im not as familiar with motherboard caches though so I might be wrong.

The program I used to generate this graph makes steps through a large array in memory forcing the loading and unloading of data into the caches and records how long each load takes. From the graph the L1, L2, and L3 cache sizes can be found by the verticle jumps between array sizes in this case there are 3 caches and the sizes respectively are 64k, 512k and between, 4M and 8M (in this case 6M, per the processor specification). The set of lines with the highest latency are accesses to ram. This program came out of "Computer Archecture" by John Hennesy and David Patterson where they say you can find the cache sizes from a graph of this type but do not explain how at least not that I have found as of yet.