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1) A nonpipelined processor has a clock rate of 2.5 GHz and an average CPI (cycle per instruction) of 4. An upgrade to the processor introduces a five-stage pipeline. However, due to internal pipeline delays, such as latch delay, the clock rate of the new processor has to be reduced to 2 GHZ.
a. What is the speedup archieved for a typical program?
b. What is the MIP rate for each processor?


2)A microsprocessor is clocked at a rate of 5 GHz. (show work please).
a. How long is a clock cycle?
b. What is the duration of a particular type of machine instruction consisting of three clock cycles?

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What did you answer so far? what exactly don't you understand?

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