hi,
can I use two when statement in one vhdl code ?
architecure aa of a is
begin
out <= x + y when ....
x-y when.....
x;
out2 <= .......
;
end aa;
hi,
can I use two when statement in one vhdl code ?
architecure aa of a is
begin
out <= x + y when ....
x-y when.....
x;
out2 <= .......
;
end aa;
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