Signal assignment in VHDL

[hg_fs2002]

I'm trying to assign a signal to another signal, I don't get any error. However, when I simulate my code the R0 and IR signals are UUUUUUUU while my port mapping does not have any problem and doutt signal is correct.

component RAM is port
(       address : in std_logic_vector(7 downto 0);
        rw : in std_logic;
        din :in std_logic_vector(15 downto 0);
        dout :out std_logic_vector(15 downto 0));
            
 end component  RAM;
  
  begin
    PC<="00000000";
   RAM1:RAM port map( rw => rww , din => dinn , address => addresss , dout => doutt );
    rw <= '0';
-- Fetch
   process (start,CS)
      
     begin
       
       case CS is
      when S0 =>
       if start='1' then
       rww<='1';
       addresss <= PC;
       IR <= doutt ;
      
       NS<= S1;
       else
       NS<=S0;
       end if;
--Decode      
     when S1 =>
       Command <= doutt(3 downto 0);
       -- load 
       if command="0000" then
          addr<= doutt( 13 downto 6);
          rww<='1';
          addresss <= addr;
          R0 <= doutt;
          NS<=S2;
       end if;
-- Execute
          
   when S2 =>
     
      output<=R0;
      y <= conv_integer (PC) + 1;
      PC <=conv_std_logic_vector (y,8);
       
     end case;
   end process;