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What is the algorithm to check one gate's output to be stuck-at-1 or stuck-at-0 ? Thanks in advance.

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For : "stuck-at" means a node is permanently 0 or 1. Two practical ways to check a single gate output are (A) exhaustive simulation and (B) targeted ATPG-style reasoning. 's reaction is understandable — this is digital-test terminology — and 's link points toward more formal material. The short practical guidance below is focused on combinational gates; sequential circuits need time-frame expansion or scan chains.

A simple, guaranteed method for small circuits is brute-force simulation:

for vector in 0 .. (1<<N)-1:
    apply_vector(vector)
    y_good = simulate()
    y_sa0  = simulate_with_node_forced(node, 0)
    y_sa1  = simulate_with_node_forced(node, 1)
    if y_good != y_sa0: note vector detects stuck-at-0
    if y_good != y_sa1: note vector detects stuck-at-1

If a detecting vector is found, the corresponding stuck-at fault is observable. If none is found the fault may be redundant or requires sequential setup.

For larger circuits use targeted ATPG reasoning: (1) sensitize the faulty node so the good circuit produces the opposite value (e.g., to detect stuck-at-0 force the gate output to 1 by choosing its inputs appropriately); (2) choose a propagation path to a primary output and assign non-controlling values to side inputs along that path so the discrepancy travels to the output. Use D/D' notation for bookkeeping. Common controlling/non-controlling values: AND (controlling=0, non-controlling=1), OR (controlling=1, non-controlling=0); NAND/NOR invert the output logic. If ATPG fails, the fault may be redundant. See standard references on the stuck-at fault model and automatic test-pattern generation for formal algorithms and proofs: Stuck-at fault, Automatic test pattern generation.

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Member Avatar for Ancient Dragon

What in the world are you talking about???

Member Avatar for ddanbe

Maybe ?

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