I have begun a new project in MIPS64 assembly language. I wrote MIPS assembly three times previously (and other MIPS CPUs too), but have pretty much forgotten the specifics. But I remember thinking the person who created the instruction set was "thoughtful" in his choices (quite an admission for someone who also designed CPUs back when).
However, now that I refer to instruction set information as I start to write some crucial inner loops, I am either mis-reading the documents, or I am struck by what appears to be a significant error in judgement. Can someone writing MIPS64 confirm which is correct - or refute both.
I refer to the apparent lack of scaled [offsets] in indexed addressing. Since the architecture requires size-aligned memory addresses, why would the offset not be left-shifted by 0,1,2,3-bits before adding to the base address when accessing 8,16,32,64-bit data-types? To not scale means you reduce the number of elements you can access with immediate offsets and sub-64-bit variable offsets by 1,2,4,8 times AND make possible memory-alignment faults that are utterly pointless.
So, did I misread MIPS64 documents and offsets are ALWAYS scaled? Or did the designer have a lapse in judgement? Or (make me blush), do I miss some purpose in this choice - that is more important than the advantages I noted above?
PS: Anyone else programming the XLS [or XLR] chips from RMI, or similar octeon chips from cavium??? I have another question about external memory access speeds/capabilities [static / dynamic RAM].