I have to do a group report about the Transmeta Efficeon Processor, and I chose to cover aspects about the instructions that it impliments. The report has to cover certain things, and I am having difficulty find information about "instruction fetch and execution cycles and timing (including details of pipelining, if applicable);" Could someone help me out with this?

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Last Post by BigPaw

Unfortunately I had already looked there and none of those websites helped. Basically, I need to know the instruction execution cycle and the average IPC (not the maximum IPC).


Transmeta processors have a different architecture to yourMove typical processors, so it may help to know what it is you want to do. But, that said, there's no obligation.

Here's another helpful guide that may come in useful somewhere down the line in your project.

Transmeta Efficeon BIOS Programming Guide


Already looked there too, and t did not answer my questions. I just need to know what the actual instruction execution cycle is for the Transmeta Efficeon Processor (I know that it requires 4 stages to translate x86 instructions to VLIW instructions, and then 6 more stages to execute the instructions; however, I do not know what the basic commands the Efficeon executes in order to those stages). I also need to know what its average performance rate is (I found this article where this guy tested the Efficeon using 2 seperate benchmarks and got an average IPC, but I don't know how universal those average IPCs are).


We're not beaten yet... have you tried contacting Dave Ditzel? He was co-founder and Chief Technical Officer of Transmeta in it's glory days.

David Ditzel

You will need to sign up to Linkedin to contact him, or he may also have a Facebook Page. There may be other means if you Google him.

The features of this processor you are looking for may be something they want to keep under wraps, but hopefully not.


I sent him a private message, so hopefully he will reply. Thanks for your help.

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