0

My process involves:

- Run Make on a c++ file and generate a binary file
- Run readelf on binary file generated and dump contents in HEX form into NEW_File
*- Import data from generated file into c++ file vector as 8 bit hex words
*- other VLSI related sections

*implemented

After a ton of help from some very helpful people on this site I have the last step complete but now I would like to carry out the other two automatically. The current structure of my project is:

C++ top file emulates OS
-->Verilog file ("MIPS.v") emulates MIPS I processor
---->Other verilog modules are instantiated within MIPS.v file

Ideally I want to have my c++ file structured in the following way

main()
{
compile c++ file
run readelf on c++ file and dump into NEW_File
fill vector accordingly
(...other VLSI related sections...)
}

Is there a way to do the first two steps within my c++ file?

2
Contributors
2
Replies
3
Views
7 Years
Discussion Span
Last Post by dansnyderECE
1

Yes it is possible, although I'd recommend automation via make and a shell script. For example, add two targets to a makefile:

simulate: NEW_file
    simulation command line here

NEW_file: binary_file
    reader command line here

( simulate target should be a default one).

If the simulation generates output, you may want to have that output file as another target.

This topic has been dead for over six months. Start a new discussion instead.
Have something to contribute to this discussion? Please be thoughtful, detailed and courteous, and be sure to adhere to our posting rules.