So one of my assignments is to code a MAKEFILE program. Though we discussed this over in class I'm not sure exactly sure how it works. Here's one of the examples we went over:

----------------------------------------------------------------------------- #
# DELDIR  makefile 
#    Old-style MAKEFILE format.  Microsoft MAKE  V1.x 
#    Similar to CSC3350 Lab Assignment 
 ----------------------------------------------------------------------------- #
 ###############################################################################
# Targets 
findfile.obj: findfile.c 
 cl  /c  findfile.c 
setdta.obj  : setdta.c 
 cl  /c   setdta.c 
deletes.obj: deletes.c  deldir.h 
  cl  /c  /Zid deletes.c 
deldir.obj:  deldir.c  deldir.h 
 cl  /c   deldir.c 
deldir.exe:  deldir.obj  findfile.obj  setdta.obj  deletes.obj  
 cl  /Zid  deldir.obj  deletes.obj  findfile.obj  setdta.obj

So this is called a "script"? Does that mean this is what the code looks like? Also, how does each line function? If someone could explain this to me I would be very grateful.

Thank you!

J

> So this is called a "script"?

No. This is called a makefile.

> Does that mean this is what the code looks like?

Can you clarify the question?

> Also, how does each line function?

deletes.obj: deletes.c  deldir.h 
  cl  /c  /Zid deletes.c

The first line tells the make utility when to rebuild the target. It says that deletes.obj depends on deletes.c and deletes.h. In other words, if any of the dependencies is newer than the target (say, you edited deletes.c), the target (deletes.obj) must be rebuilt. Otherwise, the target is intact, and should be left as is.
The second line (aka recipe) tells how to rebuild the target.

Other line pairs follow the same pattern.

Make is different in a couple of ways from most programming and scripting languages: You don't describe how to do what you want (procedural languages) but instead give transformation rules, then ask for what you want (declarative languages).

The makefile syntax/format is also odd (though if I recall correctly the Microsoft version is a little less stringent) in that the body of a rule must be indented with a single leading tab.

There are lots of good tutorials. Go read one or two of them. Once you wrap your mind around the way make works, you will find it both reasonably easy and useful (though IDEs can do most of the work for you if you use one)

A make "script" is usually called "makefile" since they really aren't acripts as such.

Thanks for the help! I was reading through one of the tutorials I found and it mentioned that I could potentially change the name of the makefile command through a command line option and was curious on how to do that.

So for example, instead of typing in "makefile target.exe" I would want "S_MAKE target.exe" how would I change that?

Actually, the command is make[I](.exe)[/I] . By default, make looks for a file in the current working directory named either "makefile" or "Makefile" (on systems where case counts in filenames). You change the name that make looks for by adding -f somename or --file=somename on my version of make (I use OS/X with GNU Make). Your make may allow other variations. Invoking make --help will probably tell you what you need to know.

Your system may also have other versions of make. Some compiler vendors offer extended or specialized versions of make, sometimes with other names.

So, for a vanilla situation, to use a makefile named S_MAKE, I would invoke from the command line like this: make --file=S_MAKE target.ext

Edited 5 Years Ago by griswolf: n/a

as far as I know, make files are used to compile codes. any thing on the ledt hand side of the ':' in a line is supposed to be derived. anything on the right hand of the ':' are used to create the file on the left. just like '=' in c.

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