Doubts with sidt instruction.

Hi Friends! I have a doubt with the sidt instruction. The Intel documentation for “SIDT m”

Stores the content of the IDTR in the destination
 operand. The destination operand specifies a 6-byte memory location.
If the operand-size attribute is 32 bits, the 16-bit limit field of
 the register is stored in the low 2 bytes of the memory location and the 32-bit base address is stored in the high 4 bytes.

DEST[0:15] <- IDTR(Limit);

DEST[16:47] <- IDTR(Base); (* Full 32-bit base address stored *)

I don't understand why they talk about operand-size attribute of 32 bits, when they say that the destination specifies a 6-byte (48 bits ) memory location. Can someone explain me this??

I am new with assembly code. Thank you very much!!!

5 Years
Discussion Span
Last Post by NotNull

The operand size attribute is apart of the instructions opcode
and specifies 8-bit, 16-bit, or 32-bit operands.

The IDTr register contains the 32-bit linear address of the Interrupt Descriptor
Table and a 16-bit Limit Field, which specifies the number of entries in this

Though 6 byte operands are not usual 32-bit protected mode far pointers are
48-bits, even though the IDTr does not contain a 48-bit far-pointer.

The SIDT and LIDT instructions are used to store and load the contents of the IDTr.

If storing the contents of the IDT register and the operands are 32-bits,
it will store a 32-bit linear address and 16-bit limit at the location referred
to by its operand.

; Assuming sufficient privileges to access the IDT register
SIDT DWORD [Intr_Desc_R] ; 32-bit SIDT instruction

Intr_Desc_R DB 6 DUP(?) ; 48-bit storage location
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