The triple-gate transistor is not new, almost exactly three years ago on June 12th 2003 at the Symposia of VLSI Technology and Circuits in Kyoto, Japan, Intel was heralding it as the future of chip design. However, the fact that at the same Symposium this week in Hawaii, Intel reveals the technology is moving out of the conceptual research phase and could be used in chip production as soon as 2010 most certainly is newsworthy.
Intel has successfully built the transistors which use gates on three sides to control current: a structure that reduces leakage (so less overheating and less power consumption) while allowing more electricity to flow (so it runs faster). By comparison, the planar transistor used in chip construction today only has current flowing through one side. According to Mike Mayberry, Director of Components Research and Vice President of Technology and Manufacturing at Intel, this will mean processors that use either 50% less off-current or a 45% speed increase when compared to the current batch of 65nm process transistors. The end result being 35% less power consumption at a constant speed.
Why does this appeal to the geek in me? Two words: Moore’s Law. Many engineers have been happily announcing the end of the infamous 41 year old remark that that the number of transistors on a chip doubles roughly every two years (Moore himself insists he never said 18 months, although this has become the generally accepted interpretation of Moore’s Law). This on the basis that when you get to chip geometry below 90nm the amount of electrical leakage increases, making the processors non-viable. The multiple, but slower, core path has been seen as the route most likely to succeed. Until now that is. Suddenly the Intel co-founders remarkably perceptive observation about silicon integration looks like it has a new found longevity thanks to the triple gate development. Mayberry is suggesting that it means chips can be scaled down to the sub 45nm realm, possibly even to 22nm, as we enter the next decade. Intel has already announced plans to move to 45nm geometry chips in 2007 and 32nm in 2009.