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The triple-gate transistor is not new, almost exactly three years ago on June 12th 2003 at the , Japan, was heralding it as the future of chip design. However, the fact that at the same , Intel reveals the technology is moving out of the conceptual research phase and could be used in chip production as soon as 2010 most certainly is newsworthy.

Intel has successfully built the transistors which use gates on three sides to control current: a structure that reduces leakage (so less overheating and less power consumption) while allowing more electricity to flow (so it runs faster). By comparison, the planar transistor used in chip construction today only has current flowing through one side. According to Mike Mayberry, Director of Components Research and Vice President of Technology and Manufacturing at Intel, this will mean processors that use either 50% less off-current or a 45% speed increase when compared to the current batch of 65nm process transistors. The end result being 35% less power consumption at a constant speed.

Why does this appeal to the geek in me? Two words: Moore’s Law. Many engineers have been happily announcing the end of the infamous 41 year old remark that that the number of transistors on a chip doubles roughly every two years (Moore himself insists he never said 18 months, although this has become the generally accepted interpretation of Moore’s Law). This on the basis that when you get to chip geometry below 90nm the amount of electrical leakage increases, making the processors non-viable. The multiple, but slower, core path has been seen as the route most likely to succeed. Until now that is. Suddenly the Intel co-founders remarkably perceptive observation about silicon integration looks like it has a new found longevity thanks to the triple gate development. Mayberry is suggesting that it means chips can be scaled down to the sub 45nm realm, possibly even to 22nm, as we enter the next decade. Intel has already announced plans to move to 45nm geometry chips in 2007 and 32nm in 2009.

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As pointed out, the multi‑gate idea was the seed for the move away from strictly planar transistors. The practical payoff is straightforward: by raising a thin silicon "fin" and placing the gate on three sides, a tri‑gate/FinFET gives much tighter electrostatic control of the channel. That stronger control is what cuts off‑state leakage and lets designers run at lower voltages or higher performance without the same short‑channel problems that plague planar MOSFETs. (spectrum.ieee.org)

Intel took that concept out of the lab and into production for its 22 nm generation (the Ivy Bridge family), marking the industry’s first high‑volume use of a 3‑D gate transistor. The move validated the idea: the extra fabrication complexity paid off in energy and scaling benefits for mainstream CPUs. (wired.com)

After Intel’s production ramp, FinFET variants became the default for leading nodes across the foundry ecosystem. Major foundries and vendors standardized around multi‑gate designs for the generations that followed, and more recently the industry has been evolving again toward gate‑all‑around (GAA) nanosheet variants at the very smallest nodes (Samsung began shipping a GAA‑based 3 nm family while other vendors pursued different timing and flavors of GAA vs. FinFET). That evolution shows the pattern: new device geometry buys headroom, but it also shifts the set of engineering tradeoffs. (en.wikipedia.org)

Practical takeaway: tri‑gate/FinFET extended Moore’s Law in a real, adopted way, but it did not remove the hard work. Designers and tool flows had to absorb new PDK rules, IP requalification, SRAM and variability challenges, and increasing lithography/DTCO complexity as nodes shrank. For anyone following the thread from 2006, the key is this — the concept worked, the industry adopted it, and the push to stay in the lead simply moved the problem set rather than eliminating it. (anandtech.com)

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