Hi I'm new and have a question regarding MIPS hardware single cycle datapath. I've search and looked through many textbooks and I couldn't find the answer to my question. My question is how does a shift instruction (srl, sll, etc.) get interpreted and travel through a single cycle datapath. Everything I come across acknowledges various R type, J type and I type instructions, but never explains the shift instruction in particular, which doesn't seem to be compatible with all the single cycle data path models given. There is a 16 bit immediate field into an extender for I type instructions, so the only way it even seems remotely possible for a shift instruction to work is if the 5 bit shift amount field somehow goes into this extender. So basically, my question is where does the 5 bit shift amount field go into in a single cycle datapath. Here is an example of a model, all models I've looked at follow this similar structure. http://www.cse.lehigh.edu/~mschulte/ece201-02/lect/lec08.pdf#search=%22mips%20single%20cycle%20data%20path%22

What I'm leaning towards thinking is that there is a separate module that is not presented that handles shift instruction. Any help or clarification would be greatly appreciated, thanks.

It just happens in the ALU. The op and funct bits for SLL are all 0, btw. Also, NOP is treated as SLL r0, r0, 0.

So where does the 5 bit shift field feed into? Does it feed into the 16 bit immediate line by getting sign extended to 16 bits, then get sign extended again to 32 bits to go into the ALU? Thanks for your time.

To be honest, I don't exactly remember how it works. I doubt it uses the 16-bit extender, though, since it's not an I type instruction. I want to say that there's a mux (and probably a 5-to-32 bit extender) between the register file and the ALU, but I really can't remember for sure. I do know that it uses the ALU for the operation though.

i need a block diagram of single cycle mips datapath
for deploying in max-plusII. and when i design it in maxplus,
i recieved an error "Project has no output or bidirectional pins in the top-level design file" please help me in correcting this design.

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