how to tell more than one include folders to the compiler

Makefile :

CC              = gcc
CFLAGS          = -I../include
HVFUTILCFLAGS   = -I/home/empress/HamVeriFeeder/hvfutil/include/
all: HVFE.o RdbMapping.o BUFR_Encoder.o
        rm -f BUFR_Encoder.o HVFE.o RdbMapping.o ../lib/libhvfe.a *.bufr *.dat
BUFR_Encoder: BUFR_Encoder.o
        $(CC) -g -c BUFR_Encoder.c $(BUFRENCODER_CFLAGS)
        $(CC) -g -c HVFE.c $(CFLAGS)
RdbMapping: RdbMapping.o
        $(CC) -g -c RdbMapping.c $(CFLAGS)

when i make it says:
gcc -I../include -c -o BUFR_Encoder.o BUFR_Encoder.c
BUFR_Encoder.c:15:23: ArrayUtil.h: No such file or directory
make: *** [BUFR_Encoder.o] Error 1

BUFR_Encoder.c could not be compiled, because an included header(ArrayUtil.h) cannot be found.

why doesn't it see the HVFUTILCFLAGS?

you can have as many -I flags as you want -- just put a space between then on that CFLAGS line

then why can't the compiler see

Can't we assign variables in Makefile? Variables assigned in Makefile seems to be empty sometime. So for example compiler can't see the include folder assigned to the variable with -I.

There's something else wrong with your makefile then

> $(CC) -g -c BUFR_Encoder.c $(BUFRENCODER_CFLAGS)
Because the command you got, looks nothing like this
gcc -I../include -c -o BUFR_Encoder.o BUFR_Encoder.c

In other words, it seems you got the default .c.o make rule to turn a .c file into a .o file.

Are you sure your actions are indented with a single TAB character. Make can be very fussy about such things.

Posting to the forum as inline text is probably going to corrupt this delicate bit of information, so perhaps attach your makefile as an attachment, so we can see byte-for-byte what you have.

i've attached the makefile.