100-Core Processor on Tap

EddieC 1 1K Views

Thought you were bleeding edge with your quad-core PC? Think again. A company called Tilera today announced that it's working on a chip containing 100 processor cores, which it says could be seen by 2011. It's part of its new TILE-Gx line of 64-bit multi-core processors, the first of which--a 36-core chip--will be sampling by the end of 2010, the company said today in a . With its top-end TILE-Gx100, Tilera claims to outstrip Intel's next-generation Westmere processor in performance-per-watt by a factor of 10. Other models will contain 16 and 64 cores, and will sample in early 2011.

But all those cores won't do much good without applications to exercise them, right? So Tilera also offers Multicore Development Environment, a simplified multi-core Eclipse-based IDE that can target SMP Linux 2.6, Zero Overhead Linux, Bare Metal Environment and hybrid systems. The package includes an ANSI C/C++ compiler, system simulator, GNU command line tools and graphical multi-core application debugging and profiling.

The breakthroughs in multi-core technology are the result of an architecture under development since 1990. TILE-Gx chips share local cache across all cores, and a proprietary two-dimensional interconnect eliminates the need for an on-chip bus.

“We believe this next generation of high-core count, ultra high-performance chips will open completely new computing possibilities,” said Tilera CEO Omid Tahernia, a 21-year veteran of Motorola who joined Tilera in 2007 after running the DSP division of Xilinx. “Customers will be able to replace an entire board presently using a dozen or more chips with just one of our TILE-Gx processors, greatly simplifying the system architecture and resulting in reduced cost, power consumption, and PC board area. This is truly a remarkable technology achievement...[and] ushers in a new era of many-core processing.” Tell me, Tilera, would that be the "Tile Era?"

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As pointed out, many-core silicon forces the hard work into software: the OS, runtimes and applications must be written to avoid global contention and to exploit data locality. Practical priorities are sharding state (per-core queues or sharded caches), preferring message-passing or lock-free handoffs for hot paths, and batching updates so synchronization cost is amortized.

Kernel-level techniques that scale well on high core counts include per-CPU data (to avoid cache-line bouncing), RCU for read-mostly access with asynchronous reclamation, and sequence counters/seqlocks for very low-overhead readers with writers that can tolerate retries. Each of these is documented in the Linux kernel tree and should be considered when designing subsystems that must scale to dozens of cores. (kernel.org)

For application authors and sysadmins, pinning and isolation reduce migration and cache-warmup costs. Use taskset for quick runs and sched_setaffinity/pthread_setaffinity_np for programmatic control; the example below shows a small pthread binding to CPU 3:

#include <pthread.h>
#include <sched.h>
#include <stdio.h>

void *worker(void *arg) {
    cpu_set_t cpuset;
    CPU_ZERO(&cpuset);
    CPU_SET(3, &cpuset); /* bind this thread to CPU 3 */
    if (pthread_setaffinity_np(pthread_self(), sizeof(cpuset), &cpuset) != 0)
        perror("pthread_setaffinity_np");
    /* CPU-bound work here */
    return NULL;
}

int main(void) {
    pthread_t t;
    pthread_create(&t, NULL, worker, NULL);
    pthread_join(t, NULL);
    return 0;
}

Use affinity alongside isolcpus/cpuset for larger deployments, and always measure: profile with perf/ftrace to find lock hotspots, then refactor those hot paths (shard, batch, or convert to read-mostly patterns). (man7.org)

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