Sorry if this is in the wrong place, i would like to just verify if what i did correct, because there were times, i felt i completely did this correct, but when ever i would get test/hw back it would come back incorrect so if somebody else wouldn't mind double checking this for me that would be great, thank you!
ok i have a question, im not sure whether im correct or not, if anybody could verify what i have is correct i would be very thankful. here is the answers i got, following the question
CPI- A: 8.66 B: 8
MIPS - A:90.64665127 B: 98.125
execution Time- A:110.318473 ms B: 101.910828 ms
speed up- 1.082500017 resulting in a very slight speed up
* for Chip B, the new table i made only changed for "floating point" i split it into two, like so:
.
.
|FLOATING POINT | 11% | 14 cycles
|FLOATING POINT2 | 11% | 8 cycles
Actual question:
Consider a machine with a processor that runs at 785 MHz and an instruction mix for a benchmark program used to evaluate that machine:
| INSTRUCTION TYPE | FREQUENCY | CYCLES
--------------------------------------…
|LOADS & STORES | 10% | 18 cycles
|INTEGER ARITHMETIC | 53% | 6 cycles
|FLOATING POINT | 22% | 14 cycles
|CONTROL TRANSFER | 15% | 4 cycles
--------------------------------------…
The hardware design team is trying to improve performance. the team has found a way to reduce the number of cycles required for floating point division/ multiplication, but doing so will require an overall slowdown for the processor by increasing cycle time by 18 %. it is your job to conduct the analysis to see if this change is worthwhile. floating point division/ multiplication is 1/2 (half) of all floating point operations. if the change is implemented, floating point division/multiplication will require only 8 cycles per instruction. the remaining floating point operations will still require 14 cycles per instruction. All other operations will require their original number of cycles to complete.
lets call teh two versions of thsi processor Chip A and chip B. chip A ist he orginal version, Chip B is the new design. calculate the following
(a) calculate CPI for chip A and B
(b) calculate MIPS for chip A and B
(c) calculate execution times for chip A and B running the benchmark program, assuming the program consists of 10,000,000 instructions
(d) is there a speed up or slow down, show speed up ratio supporting your answer, is it worth while or should it be scrapped
