which of the following besr describe a VonNeuman Architecture cache?
1. a cache where each data item can be asssigned to any block as needed.
2. a cache where the last n-bits of a block address denotes which group of cache line are used.
3. an arrangment where data and instructions appear int eh same cache.
4. an arrangment where the data and instruction cache are separated.
5. a cache where the assignment of data intems to catch lines is determined by last n-bits of the data items address..
i would like to know the answer of this question was in my exam just curious about it
Thank you