Hello folks,
I'm new to daniweb and I look forward to the experiences I will have here. I'm a junior pursuing a CS degree and can't wait to see what's in store for me. I know you guys have a strict homework policy and it is why I have given it some thought and looked over my notes before I went on and posted this up. Hopefully, I get pointed in the right direction...
It's a question related to an operating systems course. Maybe the question isn't well posed, but here it goes:
Assume that the interrupt vector (IV) is wiped out - it has become all zeros, and assume that any legal instruction has a "1" as a leftmost bit. The user executes a system call. What happens?
My approach:
I know that an OS maintains a table, which is the interrupt vector. This table associates each interrupts's ID with the starting address of its service routine. I also know that the mode bit (in PSW) must be switched from USER mode = 0 to SUPERVISOR mode = 1 to service the interrupt after the system call. In addition, all the values of the PC and PSW need to be saved to a segment of the IV. But I'm not understanding the connection between them...
If we consider, for example an interrupt handling sequence in an I/O device, the typical steps in the process would be:
1. The device issues interrupt signal to the processor...
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2. Before the processor responds to the interrupt, it finishes the execution of the current operation...
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3. Now, the processor tests for a pending interrupt request. If there is one, it sends an acknowledgement signal to the device that issued the interrupt so that it allows the device to remove the interrupt signal.
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4. At this stage, the processor needs to prepare to transfer control over to the interrupt service routine (ISR). This is where other branching factors come in to play and probably where I might be missing some "under the hood" details. So, all the information needed to resume the program at the point of interrupt is saved. The current program counter (PC) and program status word (PSW) are also saved on to the stack. Then the processor loads the PC with the entry location of the interrupt handling routine that will respond to the particular interrupt.
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5. At this point we'll just say that the interrupt handler is able to process the interrupt...
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6. Once it completes, we need to restore the saved program counter and PSW values. I think that here, the mode bit needs to be changed back to USER mode from the SUPERVISOR mode before we "pick up where we left off" (e.g., the next instruction that is executed is continued from the interrupted program).
The overall system call instruction and interrupt handling sequence is a bit complex and it is easy to leave off an extremely importand detail, or else things can go wrong (which is where I think my problem is). To my understanding, the interrupt vector is native to the OS and like I mentioned above, it is the table that relates the ID's of the interrupt handlers to their starting ISR addresses. Ok, so could it be that the question is referring to a wipeout of the ID's in the interrupt vector (which can be done if you want to change how a particular interrupt is handled) and consequently not being able to handle the system call? Please don't feel overwhelmed after taking the time to read this post, but I would really appreciate it if something, if not anything is replied.:D
Thank you in advance....