I am working on the following problem

You are asked to optimize a cache design for the given references. There are three direct-mapped cache designs possible, all witha total of eight words of data: C1 has one-word blocks, C2 has two-word blocks, and C3 has four-word blocks. In terms of miss rate, which cache design is the best? If the miss stall time is 25 cycles, and C1 has an access time of 2 cycles, C2 takes 3 cycles, and C3 takes 5 cycles, which is the best cache design?

List of 32-bit memory address references, given as word addresses.

a) 1, 134, 212, 1, 135, 213, 162, 161, 2, 44, 41, 221
b) 6, 214, 175, 214, 6, 84, 65, 174, 64, 105, 85, 215

I know the answer for the miss rates are

C1 = 3%
C2 = 2%
C3 = 1.2%

I have not been able to figure out how these are calculated?

Edited by coolbeanbob: n/a

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Last Post by Rashakil Fol

This is homework from a textbook. I believe there is a way to mathematically calculate the miss rates? Is this correct?

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