ADC giving uneven result?

[riccardo-m]

Hi,

I have a circuit that charges a capacitor and discharges it. The length of the discharge pulse is supposed to be determined by the ADC value from a POT. The pot is wired as a voltage divider and I have tested that the voltage to the pic pin varies nicely from 0V to 5V,

But it seems to only sort of work Huh

I'm using a PIC12F675 which has a 10-bit ADC. I'm just using the ADRESH byte so that it works pretty much like an 8-bit ADC.

As I turn up the voltage, initially the pulse time is still at minimum. When almost at the middle, the time jumps suddenly to a higher value, then again later until maximum at 5V.

So it is as if there's only about 4 possible input values rather than 256. It must be something in my code, either the reading of the ADC, or using the ADC result for making the delay. Please take a look below and tell me if there's anything obvious there..

ADC configuration...

BCF STATUS,RP0 				; BANK 0
	BCF ADCON0, ADFM			; Left justified (clear and use just ADRESH for an 8bit result)
	BCF ADCON0, VCFG			; Vdd reference
	BCF ADCON0, CHS1			; Set AN0 as analogue input
	BCF ADCON0, CHS0			; Set AN0 as analogue input
	BSF STATUS,RP0 				; BANK 1
	MOVLW b'00010001'			; Fosc/8 (2us), AN0 is selected for reading
	MOVWF ANSEL

When the cap is charged, a digital input triggers this routine...

DISCHARGE
	BSF DISCHARG				; DISCHARGE
	CALL READPOT
	CALL WAITPOT
	CALL READPOT
	CALL WAITPOT
	BCF DISCHARG				; END DISCHARGE
	RETURN

The ADC routine...

READPOT
	BSF ADCON0, ADON			; Enable AD
	BSF ADCON0, GO				; Start AD conversion
AD	BTFSC ADCON0, GO			; TEST if conversion is finished
		GOTO AD					; Loop until conversion is done
	MOVF ADRESH, W				; High side byte from AD (8-bit)
	MOVWF POT					; Stores ns delay value in POT
	BCF ADCON0, ADON			; Disable AD
	RETURN

The delay routine...

WAITPOT
	INCF POT	; make sure not zero
WAITPOTL
	DECFSZ  POT,F		; Decrement POT
        GOTO WAITPOTL	; Loop until 0
	RETURN

[Salem]

http://ww1.microchip.com/downloads/en/devicedoc/41190c.pdf
See the table page 44.

Are you sure you're allowing enough time for a conversion to take place?

Also page 47 - A/D Acquisition Requirements
There is a minimum delay between acquisitions which your back-to-back conversions would seem to be violating.

[riccardo-m]

Ok, I see. I thought it was just for aborted conversions. I changed my code to this, but it seems to only half solve the problem :-/

The output only starts to change after the pot is turned past 50%. I understand that losing those LSB by just using ADRESH will chop off a little, but it should only be a small amount. Why might it be doing this?

Its set for 4MHz internal Oscillator, so I'm using 8 TOSC (ADCS2:ADCS0 = 001) which seems to be in range. I've tried 16 TOSC which gives the same result.

DISCHARGE
        BSF DISCHARG                         ; DISCHARGE
        CALL READPOT
	MOVF POT, W
	MOVWF TEMP				;Make temp copy of POT
	CALL WAITPOT
	MOVF TEMP, W
	MOVWF POT				;Restore temp copy of POT
        CALL WAITPOT
        BCF DISCHARG                         ; END DISCHARGE
        RETURN