Intel chips will be core of embedded

EddieC 0 255 Views

With the release yesterday of Intel's Core series of high-performance, power-efficient processors, makers of space-constrained, mobile and other embedded devices now have a new low-cost option for their designs. The multi-core CPUs, dubbed Core i3, Core i5 and Core i7, incorporate Intel's Hyper Threading technology for fast program execution, a DDR3 memory controller and high definition graphics processor. About 200 embedded designs based on the new parts are reportedly available or soon will be.

"These processors will enable more powerful high performance computers in the embedded space," said Eric Heikkila, director of embedded hardware and systems at VDC Research Group. "When these processors are sold into the embedded market, it will most likely be into embedded systems in benign environments that are running high bandwidth applications," such as those used in communications and networking systems, and in military and aerospace applications.

In an e-mail interview yesterday, Heikkila said the proliferation of Hyper threading, Intel's simultaneous multithreading technology, is likely to accelerate the adoption of multicore parts, for which programming is complex. Hyper Threading was previously available only in Atom, Pentium 4, Xeon and the 45nm i7 processors. "Often times in applications where multicore processors are deployed, some of the cores are sitting idle because programmers simply don’t know how to utilize them all at once," he said. "But multicore processors are still used because that’s what Intel and AMD are selling." As multicore processors become mainstream, programmers won't have much choice but to learn how to take advantage of them, he said. "And experience will likely trickle down from high performance applications, the initial market for these processors, and where there is already familiarity with maximizing multiple cores and threads.

Pricing for the Core i3 for embedded applications starts at US$133 in quantities of 1000.

Dani AI

Generated

— practical follow-up for engineers evaluating mainstream Intel client cores in embedded systems.

Adopting higher‑performance client CPUs for space‑constrained or mobile appliances brings real benefits, but it changes the engineering tradeoffs. Priorities that need explicit verification are (1) thermal/TDP and cooling for sustained workloads, (2) predictability and real‑time behaviour, (3) firmware/driver maturity for the chosen OS, (4) platform I/O and chipset features, and (5) lifetime/supply commitments from the vendor. Intel now publishes embedded/edge product options and long‑life availability notes for Core‑class parts. (intel.com)

Hyper‑Threading (SMT) raises throughput but shares execution resources and can increase scheduling jitter; for latency‑sensitive or hard real‑time threads it is common to disable SMT in BIOS or via kernel boot flags (for example Red Hat’s low‑latency profile uses nosmt). Use SMT when raw throughput matters, but validate jitter and tail latency in your workload. (edc.intel.com)

Thermal design is critical: pick SKUs and package types that match worst‑case sustained power, follow Intel’s embedded thermal/mechanical guides, and test in the highest expected ambient. Consider configurable‑TDP modes and prefer designs where chassis cooling and airflow are controlled and repeatable. (manuals.plus)

Start with profiling and small, repeatable microbenchmarks before parallelizing. Pin latency‑sensitive threads to physical cores and reserve CPUs for background work. Examples:

# run process on logical CPUs 0 and 2
taskset -c 0,2 ./my_realtime_app
#define _GNU_SOURCE
#include <pthread.h>
#include <sched.h>

void pin_self_to_core(int core) {
  cpu_set_t cpus;
  CPU_ZERO(&cpus);
  CPU_SET(core, &cpus);
  pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpus);
}

Use CPU affinity tools and the pthread affinity APIs as part of acceptance tests. (man7.org)

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