Who wants nanoscale MEMS inside their CMOS wafer?

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The answer is Baolab Microsystems which has today announced its NanoEMS technology to do just that, construct nanoscale Micro Electro Mechanical Systems (MEMS) within the structure of a CMOS wafer rather than building on the surface like current techniques. This, says Baolab, means that because it uses less process steps but standard high volume CMOS lines, will reduce the manufacturing costs of a MEMS by up to two thirds.

Using the existing metal layers in a CMOS wafer to form the MEMS structure using standard mask techniques, the NanoEMS process etches the Inter Metal Dielectric (IMD) through the pad openings in the passivation layer using vapour HF (vHF). This etching process uses readily available equipment for volume production, taking less than an hour to complete. As only standard CMOS processes are used, NanoEMS MEMS can be directly integrated with active circuitry as required.

Baolab has successfully created MEMS devices using standard 0.18um 8” volume CMOS wafers with four or more metal layers, and has achieved minimum feature sizes down to 200 nanometres. This is an order of magnitude smaller than is currently possible with conventional MEMS devices, bringing the new NanoEMS MEMS into the realm of nanostructures, with the additional benefits of smaller sizes, lower power consumption and faster devices.

"We have solved the challenge of building MEMS in a completely different way" explained Dave Doyle, Baolab’s CEO. "Existing MEMS technologies are slow, expensive and require specialist equipment. They have to be either built on top of the wafer at a post production stage or into a recess in the wafer. By contrast, our new NanoEMS technology enables MEMS to be built using standard CMOS technologies during the normal flow of the CMOS lines".

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As noted, the idea of building MEMS inside the metal/dielectric stack instead of as a post‑process layer is attractive — but integration is what makes or breaks a product. Below are focused, practical points to check and a short evaluation workflow so teams can judge whether a foundry/process is suitable for a real design effort.

Why it matters: co‑fabrication can reduce interconnect parasitics, shrink package/board area, and enable tighter coupling between sensors/actuators and their readout. It also shifts many failure modes into the fab domain, so process transparency and qualification become critical.

Key questions to ask the foundry or integrator:

  • Provide a complete PDK and cross‑section showing every BEOL/metal/dielectric layer, layer thicknesses and thermal limits.
  • Describe the release etch: method, byproducts, particle control, and any downstream cleaning steps.
  • Give material mechanical properties and measured residual stress (mean and variation).
  • Supply DRC/DFM rules for anchors, release holes, minimum gaps, and alignment tolerances.
  • Confirm CAD/tool support for the extra layers and whether LVS/DFY flows are adapted.
  • List available test structures/PCMs and the recommended electrical + mechanical test program.
  • Explain wafer‑level packaging routes and environmental specs (vacuum vs. ambient, hermetic options).
  • Provide qualification data: yield impact, HTOL/thermal cycling, shock, moisture, and long‑term drift results.

Quick evaluation workflow:

  1. Get the PDK and process flow.
  2. Design a minimal test vehicle (simple cantilever/comb, anchors, test capacitors) plus electrical pads.
  3. Include PCMs and DFT features for electrical probing and SEM inspection.
  4. Run a small pilot wafer with the foundry’s suggested test plan.
  5. Measure mechanical resonances, Q, stiction, drift, and integrated readout performance; iterate.

Caution: roadmap, foundry support and proven qualification matter more than promotional claims. Plan for several design/test iterations and treat the first pilot as a qualification run rather than production-ready silicon.

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